Diagnostic method for detection of multiple defects in a Level Sensitive Scan Design (LSSD)
First Claim
1. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:
- electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;
placing the scan chain circuit into an operating region;
loading a scan test pattern into the scan chain circuit;
placing the scan chain circuit into a failing region;
applying a shift clock pulse to the clock input of the second latch;
placing the scan chain circuit into an operating region; and
unloading the scan chain.
1 Assignment
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Accused Products
Abstract
Methods of testing scan chains in integrated circuits are provided. One method may include steps of placing the scan chain circuit into an operating region, loading a scan test pattern into the scan chain, placing the scan chain circuit into a failing region, applying a shift clock pulse to the L2 (slave) latch, placing the scan chain circuit into an operating region, and unloading the scan chain. An additional step may be added to analyze the resulting data. Another method may include the steps of, placing the scan chain circuit into an operating region, loading a scan test pattern into the scan chain circuit, placing the scan chain circuit into a failing region, applying a scan clock pulse to the L1 (master) latch, placing the scan chain circuit into an operating region, applying a shift clock pulse to the L2 latch, and unloading the scan chain. An additional step may be added to analyze the resulting data.
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Citations
22 Claims
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1. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:
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electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;
placing the scan chain circuit into an operating region;
loading a scan test pattern into the scan chain circuit;
placing the scan chain circuit into a failing region;
applying a shift clock pulse to the clock input of the second latch;
placing the scan chain circuit into an operating region; and
unloading the scan chain. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:
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electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;
placing the scan chain circuit into an operating region;
loading a scan test pattern into the scan chain circuit;
placing the scan chain circuit into a failing region;
applying a scan clock pulse to the clock input of the first latch;
placing the scan chain circuit into an operating region;
applying a shift clock pulse to the clock input of the second latch; and
unloading the scan chain. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:
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electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;
placing the scan chain circuit into an operating region;
loading a scan test pattern into the scan chain circuit;
placing the scan chain circuit into a failing region;
applying a scan clock pulse to the clock input of the first latch;
applying a shift clock pulse to the clock input of the second latch;
placing the scan chain circuit into an operating region; and
unloading the scan chain. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A computer program product containing programming instructions for identifying one or more defective shift register latches in a scan chain, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input, the programming instructions comprising:
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placing the scan chain circuit into an operating region;
loading a scan test pattern into the scan chain circuit;
placing the scan chain circuit into a failing region;
applying a shift clock pulse to the clock input of the second latch;
placing the scan chain circuit into an operating region; and
unloading the scan chain.
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22. A computer program product containing programming instructions for identifying one or more defective shift register latches in a scan chain, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input, the programming instructions comprising:
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placing the scan chain circuit into an operating region;
loading a scan test pattern into the scan chain circuit;
placing the scan chain circuit into a failing region;
applying a scan lock pulse to the clock input of the first latch;
applying a shift clock pulse to the clock input of the second latch;
placing the scan chain circuit into an operating region; and
unloading the scan chain.
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Specification