Error detection and correction scheme for a memory device

• US 20050172207A1
• Filed: 01/30/2004
• Published: 08/04/2005
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Swaminathan, Shuba, Radke, William H., Keays, Brady L.
• Granted Patent: US 7,389,465 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: H03M 13/096 Checksums

Abstract

Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.

Claims

1. A method for error detection and correction in a memory device having a memory array, a data buffer, and a controller, the method comprising:

reading data from the memory array;

performing first and second error detection operations substantially in parallel;

reporting results of the first and the second error detection operations to the controller; and

storing the data in the data buffer.

2. The method of claim 1 wherein the first error detection operation is a Hamming code error detection and the second error detection operation is a Reed-Solomon code error detection.

3. The method of claim 1 wherein the first and second error detection operations are performed while reading the data from the memory array.

4. The method of claim 1 and further including:

if the first error detection operation detects an error correctable by a first error correction operation and the second error detection operation detects an error, correcting the error with the first error correction operation; and

performing the second error detection operation on the data.

5. The method of claim 4 and further including:

if the data still has the error after the second error detection operation, correcting the error with a second error correction operation.

6. The method of claim 1 and further including:

if the first error detection operation detects an error that is uncorrectable by a first error correction operation and the second error detection operation detects an error, correcting the error with a second error correction operation.

7. The method of claim 1 and further including:

if the first error detection operation does not detect an error and the second error detection operation detects an error, correcting the error with a second error correction operation.

8. A method for error detection and correction in a memory device having a memory array, a data buffer, and a controller, the method comprising:

reading data from the memory array;

performing a Hamming code and a Reed-Solomon code error detection operation substantially in parallel;

reporting results of the Hamming code and the Reed-Solomon code error detection operations to the controller; and

storing the data in the data buffer.

9. The method of claim 8 and further including:

if the Hamming code error detection operation detects an error correctable by a Hamming code error correction operation and the Reed-Solomon code error detection operation detects an error, correcting the error with the Hamming code error correction operation; and

performing the Reed-Solomon code error detection operation on the data.

10. The method of claim 9 and further including:

if the data still has the error after the Reed-Solomon code error detection operation, correcting the error with a Reed-Solomon code error correction operation.

11. The method of claim 8 and further including:

if the Hamming code error detection operation detects an error that is uncorrectable by a Hamming code error correction operation and the Reed-Solomon code error detection operation detects an error, correcting the error with a Reed-Solomon code error correction operation.

12. The method of claim 8 and further including:

if the Hamming code error detection operation does not detect an error and the Reed-Solomon code error detection operation detects an error, correcting the error with a Reed-Solomon code error correction operation.

13. A method for error detection and correction in a memory device having a memory array and a data buffer, the method comprising:

reading data from the memory array;

performing a first error detection operation on the data;

if an error is detected during the first error detection operation that is correctable by a first error correction operation, correcting the error with the first error correction operation to generate corrected data;

performing a second error detection operation on the corrected data;

storing the corrected data in the data buffer;

if an error is detected during the first error detection operation that is uncorrectable by the first error correction operation, correcting the error with a second error correction operation to generate the corrected data; and

storing the corrected data in the data buffer.

14. The method of claim 13 wherein the first error detection and correction operations are Hamming code error detection and correction and the second error detection and correction operations are Reed-Solomon code error detection and correction.

15. A memory device comprising:

a memory array;

a data buffer;

a controller circuit that is capable of reading data from the memory array and storing the data in the data buffer;

a first error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit; and

a second error detection and correction routine that operates in parallel with the first error detection and correction routine in detecting errors in the read data and communicates a second error detection result to the controller circuit.

16. The memory device of claim 15 wherein the memory array is a NAND-type flash memory array.

17. The memory device of claim 15 wherein the memory array is a NOR-type flash memory array.

18. The memory device of claim 15 wherein the first error detection and correction routine is a Hamming code error detection and correction.

19. The memory device of claim 15 wherein the second error detection and correction routine is a Reed-Solomon code error detection and correction.

20. A memory device comprising:

a memory array;

a data buffer; and

a controller circuit that is capable of reading data from the memory array and storing the data in the data buffer;

the controller executing a Hamming code error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit, the controller further executing, in parallel with the Hamming code error detection and correction routine, a Reed-Solomon code error detection and correction routine that detects errors in the read data and communicates a second error detection result to the controller circuit.

21. An electronic system comprising:

a processor that generates control signals for the electronic system; and

a memory device comprising;

a memory array;

a data buffer;

a controller circuit that is capable of reading data from the memory array and storing the data in the data buffer;

a first error detection and correction routine that detects errors in the read data and communicates a first error detection result to the controller circuit; and

a second error detection and correction routine that operates in parallel with the first error detection and correction routine in detecting errors in the read data and communicates a second error detection result to the controller circuit.