Energy-focused compiler-assisted branch prediction

• US 20050172277A1
• Filed: 01/18/2005
• Published: 08/04/2005
• Est. Priority Date: 02/04/2004
• Status: Active Grant

• Current Assignee: III Holdings 2, LLC
• Original Assignee: BlueRISC Inc.
• Inventors: Ashok, Raksit, Chheda, Saurabh, Carver, Kristopher
• Granted Patent: US 8,607,209 B2
• Time in Patent Office: Days
• US Class Current: 717/151
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3846 using static prediction, e.g. branch taken strategy
• CPC Class Codes: G06F 9/3848 using hybrid branch prediction, e.g. selection between prediction techniques

Abstract

A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.

Claims

1. A method wherein:

at compile time, control information is added to an instruction sequence prior to a control-flow changing instruction it controls;

the control information is used at runtime to control prediction of the target address of the control-flow changing instruction.

2. The method of claim 1, wherein

the prediction of a target address at runtime begins ahead of fetching the control-flow changing instruction.

3. The method of claim 1, wherein the control information is encoded in the instruction space.

4. The method of claim 1, wherein the control information is added as part of the payload in a coprocessor instruction.

5. The method of claim 1, wherein the control information is extracted at runtime before entering the processor pipeline.

6. The method of claim 1, wherein the control information includes encoding for selecting a dynamic branch prediction mechanism at runtime.

7. The method of claim 1, wherein the control information includes encoding for stalling the fetch until a control-flow changing instruction is executed.

8. The method of claim 1, wherein plural dynamic prediction mechanisms can be used.

9. The method of claim 1, wherein the control information includes encoding of a statically predicted control-flow changing instruction.

10. The method of claim 1, wherein:

the control information includes encoding of the position of the control-flow changing instruction in a sequence of instructions.

11. A processing framework that uses the method of claim 1.

12. The method of claim 1, wherein:

the control information includes encoding of a control-flow change at the end of a sequence of instructions;

the control-flow changing instruction at the end of the sequence is removed at compile time.

13. The method of claim 12, wherein:

the control information includes encoding a condition under which the control-flow change at the end of the encoded sequence should occur.

14. The processing framework of claim 1, wherein a branch target address cache is smaller in size than a second branch target address cache in the same system.

15. A method wherein:

a compile time control information is added to a control-flow changing instruction to control a branch prediction mechanism at runtime;

plural dynamic prediction mechanisms can be selected;

a control-flow changing instruction'"'"'s target address is predicted with a branch prediction mechanism and another control-flow changing instruction'"'"'s target address is predicted with another branch prediction mechanism.

16. A processing framework that uses the method of claim 16.