Optic mask and manufacturing method of thin film transistor array panel using the same

• US 20050173752A1
• Filed: 01/05/2005
• Published: 08/11/2005
• Est. Priority Date: 01/06/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Myung-Koo, Chung, Ui-Jin, Lee, Jae-Bok
• Granted Patent: US 7,858,450 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: B23K 26/066 by using masks
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0268 Shape of mask
• CPC Class Codes: H01L 21/02691 Scanning of a beam
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors

Abstract

An optic mask for crystallizing amorphous silicon comprises a first slit region including a plurality of slits regularly arranged for defining incident region of laser beam, wherein the slits of the first slit region are formed to slope by a predetermined angle to the direction of transfer of the optic mask in crystallization process, and wherein the slits of the first slit region includes a first slit having a first length and a second slit having a second length which is longer than the first length.

Claims

1. An optic mask, comprising:

a first slit region including a plurality of regularly arranged slits,

wherein the slits of the first slit region includes a first slit having a first length and a second slit having a second length which is longer than the first length.

2. The optic mask of claim 1, wherein the second length is longer than the first length by the margin of misalignment of the optic mask.

3. The optic mask of claim 2, wherein the second length is 3˜

4 um longer than the first length.

4. The optic mask of claim 1, further comprising:

a second slit region including a plurality of slits regularly arranged,

wherein the slits of the first silt region are arranged to deviate from the slits of the second slit region.

5. A method of manufacturing a thin film transistor, comprising:

forming an amorphous silicon layer on an insulating substrate;

forming a polycrystalline silicon layer by irradiating a laser beam to the amorphous silicon layer through an optic mask which includes a first slit of a first length and a second slit of a second length and translating the laser beam and the optic mask;

patterning the poly silicon layer;

forming a gate insulating layer over the semiconductor layer;

forming a gate line on the gate insulating layer to overlap the semiconductor layer partially;

forming a source region and a drain region by doping conductive impurities of high concentration on predetermined regions of the semiconductor layer;

forming a first interlayer insulating layer over the gate line and the semiconductor layer;

forming a data line including a source electrode connected with the source region and a drain electrode connected with the drain region;

forming a second interlayer insulating layer on the data line and the drain electrode; and

forming a pixel electrode on the second interlayer insulating layer to be connected with the drain electrode.

6. The method of claim 5, wherein the second length is longer than the first length.

7. The method of claim 5, wherein the first and second slits have curved boundary line.

8. The method of claim 7, wherein the first and second slits have a shape of arc.

9. The method of claim 5, further comprising a step of forming LDD regions in the semiconductor layer by doping conductive impurities having a lower concentration compared to the source region and the drain region.

10. The method of claim 5, further comprising a step of forming a blocking layer between the insulating substrate and the semiconductor layer.

11. The method of claim 5, wherein the slits are formed to slope by a predetermined angle to the direction of transfer of the optic mask.

12. The method of claim 5, wherein the optic mask includes a first slit region and a second slit region that individually include the first slit and the second slit, and wherein the slits of the first slit region and the slit of the second slit region are arranged to deviate from each other.

13. A method for manufacturing a thin film transistor array panel, comprising:

forming an amorphous silicon layer on an insulating substrate;

forming a polycrystalline silicon layer by irradiating a laser beam to the amorphous silicon layer through an optic mask which includes a first slit of a first length and a second slit of a second length and translating the laser beam and the optic mask;

forming a semiconductor layer by patterning the poly silicon layer;

forming a gate insulating layer over the semiconductor layer;

forming a data metal piece and a gate line that has a portion overlapping the semiconductor layer;

forming a source region and a drain region by doping conductive impurities of high concentration on predetermined regions of the semiconductor layer;

forming an interlayer insulating layer over the semiconductor layer; and

forming a data connection part connected with the source region and the data metal piece, and a pixel electrode connected with the drain region.

14. The method of claim 13, further comprising a step of forming LDD regions in the semiconductor layer by doping conductive impurities having a lower concentration compared to the source region and the drain region.

15. The method claim 13, further comprising a step of forming a blocking layer between the insulating substrate and the semiconductor layer.

16. The method of claim 13, wherein the slits are formed to slope by a predetermined angle to the direction of transfer of the optic mask.

17. The method of claim 13, wherein the optic mask includes a first slit region and a second slit region that individually include the first slit and the second slit, and

wherein the slits of the first slit region and the slit of the second slit region are arranged to deviate from each other.

18. A thin film transistor array panel manufacturing method, comprising:

forming a poly crystalline silicon layer by irradiating a laser beam to an amorphous silicon layer,

wherein the boundary of the poly crystalline silicon grain is aligned in a direction, and the direction is inclined from the channel direction of the thin film transistor.

19. The method of claim 18, further comprising:

forming the TFT channel direction to be inclined from the array panel.

20. The method of claim 18, further comprising:

forming the direction of the poly crystalline silicon grain to be inclined from the array panel.

21. The method of claim 20, further comprising:

forming the poly crystalline silicon with a mask that transfer inclined direction from the array panel.

22. The method of claim 20, further comprising:

forming the poly crystalline silicon with a mask that transfers parallel to the array panel and has a slit pattern inclined from the transfer direction.

23. An optic mask for crystallizing amorphous silicon comprises slits that are transparent area of laser beam and have curved boundary line.

24. The optic mask of claim 23, wherein the slits have a shape of arc.

25. A method of manufacturing a thin film transistor comprising:

forming an amorphous silicon layer on an insulating substrate;

forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer;

forming a semiconductor layer by patterning the poly silicon layer;

forming a gate insulating layer on the semiconductor layer;

forming a gate electrode on the gate insulating layer to overlap the semiconductor layer partially;

forming a source region and a drain region on both sides of the gate electrode to define a channel region therebetween;

forming a first interlayer insulating layer on the gate electrode;

forming a source and drain electrodes respectively connected to the source region and the drain region;

forming a second interlayer insulating layer on the drain electrode; and

forming a pixel electrode on the second interlayer insulating layer to be connected with the drain electrode, wherein the step of forming a polycrystalline silicon layer is performed by a SLS and grain groups formed by the SLS have boundaries deviating from the boundary of the channel region.

26. The method of claim 25, wherein the SLS is performed with using an optic mask having slits that are transparent area of laser beam and have curved boundary line.

27. The method of claim 26, wherein the slits have a shape of arc.

28. The method of claim 26, wherein the slits include a first slit and a second slit longer than the first slit.

29. The method of claim 26, wherein the slits are slanted with respect to the transportation direction of the optic mask.

30. The method of claim 26, wherein the mask has two regions having a plurality of slits that are arranged in a row and the slits of the two regions are arranged to deviate from each other.

31. The method of claim 26, further including a step of forming LDDs disposed between the channel region and the source and drain regions.