Low temperature process and structures for polycide power MOSFET with ultra-shallow source
First Claim
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1. A power semiconductor device, comprising:
- a semiconductor body of a first conductivity type;
a plurality of trenches along a surface of said semiconductor body and extending to a first depth of said semiconductor body;
a gate oxide layer lining surfaces of each of said plurality of trenches;
a gate electrode within each of said plurality of trenches, each gate electrode including a free end extending above the surface of said semiconductor body; and
a plurality of ultra-shallow source regions of said first conductivity type within said semiconductor body and extending to a second depth of said semiconductor body, wherein said second depth is approximately equal to or less than a thickness of said gate oxide layer.
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Abstract
A trench type power semiconductor device includes proud gate electrodes that extend out of the trenches and above the surface of the semiconductor body. These proud gate electrodes allow for making ultra-shallow source regions within the semiconductor body using, for example, a low temperature source drive. In addition, a method for manufacturing the trench type power semiconductor device includes a low temperature process flow once the gate electrodes are formed.
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Citations
21 Claims
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1. A power semiconductor device, comprising:
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a semiconductor body of a first conductivity type;
a plurality of trenches along a surface of said semiconductor body and extending to a first depth of said semiconductor body;
a gate oxide layer lining surfaces of each of said plurality of trenches;
a gate electrode within each of said plurality of trenches, each gate electrode including a free end extending above the surface of said semiconductor body; and
a plurality of ultra-shallow source regions of said first conductivity type within said semiconductor body and extending to a second depth of said semiconductor body, wherein said second depth is approximately equal to or less than a thickness of said gate oxide layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for manufacturing a power semiconductor device comprising the steps of:
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forming a mask layer over a surface of a semiconductor body of a first conductivity;
patterning said mask with a plurality of openings each opening extending to and exposing the surface of said semiconductor body at the bottom thereof;
defining trenches in said semiconductor body by etching said semiconductor body through said openings, each trench including sidewalls and a bottom and extending to a first depth;
forming an insulation layer on said sidewalls of said trenches;
forming a gate electrode in each of said trenches, each gate electrode including a free end and extending above the surface of said semiconductor body into a respective opening in said mask layer;
removing said mask layer, whereby each gate electrode becomes proud and extends above the surface of said semiconductor body; and
forming a plurality of source regions of said first conductivity in the surface of said semiconductor body such that each of said plurality of source regions extends to a second depth of said semiconductor body, wherein said second depth is approximately equal to or less than a thickness of said insulation layer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for manufacturing a power semiconductor device comprising the steps of:
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forming a mask layer over a surface of a semiconductor body of a first conductivity;
patterning said mask with a plurality of openings each opening extending to and exposing the surface of said semiconductor body at the bottom thereof;
defining trenches in said semiconductor body by etching said semiconductor body through said openings, said trenches extending to a first depth;
forming a gate electrode in each of said trenches, each gate electrode including a free end and extending above the surface of said semiconductor body into a respective opening in said mask layer;
removing said mask layer, whereby each gate electrode becomes proud and extends above the surface of said semiconductor body; and
forming a plurality of source regions of said first conductivity in the surface of said semiconductor body;
wherein all process steps after said removing of said mask layer are less than 900°
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Specification