Data transmission/reception system
First Claim
1. A data transmission/reception system for transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, comprising:
- a clock reception system for receiving the clock signal;
a plurality of data reception systems for receiving corresponding data signals among the plurality of data signals;
a clock transmission system for transmitting the clock signal supplied from the clock reception system to a clock signal transfer path at a small amplitude; and
a plurality of data transmission systems for transmitting the data signals supplied from corresponding data reception systems among the plurality of data reception systems to a data signal transfer path at a small amplitude, wherein the clock transmission system and the plurality of data transmission systems are respectively connected to a first power supply and a second power supply for operations, the clock transmission system includes a clock driver circuit for driving the clock signal transfer path according to the clock signal supplied from the clock reception system, and a feedback circuit for determining a high level voltage and a low level voltage of the clock signal transfer path to generate at least one control signal which is to be supplied to the clock driver circuit such that a high level voltage of the clock signal which is transmitted to the clock signal transfer path is equal to a first reference voltage which is lower than a voltage of the first power supply, and a low level voltage of the clock signal which is transmitted to the clock signal transfer path is equal to a second reference voltage which is higher than a voltage of the second power supply, and each data transmission system includes a data driver circuit for driving the data signal transfer path according to a data signal supplied from a corresponding data reception system among the plurality of data reception systems while amplitude control is performed on the data signal which is to be transmitted to the data signal transfer path based on a control signal generated by the feedback circuit.
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Accused Products
Abstract
In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.
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Citations
8 Claims
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1. A data transmission/reception system for transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, comprising:
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a clock reception system for receiving the clock signal;
a plurality of data reception systems for receiving corresponding data signals among the plurality of data signals;
a clock transmission system for transmitting the clock signal supplied from the clock reception system to a clock signal transfer path at a small amplitude; and
a plurality of data transmission systems for transmitting the data signals supplied from corresponding data reception systems among the plurality of data reception systems to a data signal transfer path at a small amplitude, wherein the clock transmission system and the plurality of data transmission systems are respectively connected to a first power supply and a second power supply for operations, the clock transmission system includes a clock driver circuit for driving the clock signal transfer path according to the clock signal supplied from the clock reception system, and a feedback circuit for determining a high level voltage and a low level voltage of the clock signal transfer path to generate at least one control signal which is to be supplied to the clock driver circuit such that a high level voltage of the clock signal which is transmitted to the clock signal transfer path is equal to a first reference voltage which is lower than a voltage of the first power supply, and a low level voltage of the clock signal which is transmitted to the clock signal transfer path is equal to a second reference voltage which is higher than a voltage of the second power supply, and each data transmission system includes a data driver circuit for driving the data signal transfer path according to a data signal supplied from a corresponding data reception system among the plurality of data reception systems while amplitude control is performed on the data signal which is to be transmitted to the data signal transfer path based on a control signal generated by the feedback circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification