MOS charge pump
First Claim
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1. A charge pump comprising:
- a plurality of stages including at least a first stage and a last stage, each of the stages comprising a first transistor having a first source terminal, a first drain terminal, a first gate terminal and a first body terminal;
a second transistor having a second source terminal, a second drain terminal, a second gate terminal, and a second body terminal;
wherein each transistor of each stage, except for the second transistor of the last stage, has its source and drain terminals connected to each other and to a body terminal of a next transistor;
wherein the first transistor of each stage has a first gate terminal connected to an alternating polarity voltage source and the second transistor of each stage has a second gate terminal connected to ground; and
wherein the first transistor of the first stage has a first body terminal connected to ground; and
the second transistor of the last stage has a second source terminal and a second drain terminal connected to an output terminal of the charge pump.
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Abstract
A passive charge pump includes a plurality of stages or a single stage, with each stage including only two MOS transistors. Both of the transistors are configured in a transcapacitance configuration, and both transistors are primarily in the accumulation mode during operation. Embodiments of the charge pump rely entirely on the MOS capacitance and its embedded diode features to perform the necessary charge accumulation and transfer process necessary for voltage multiplication at the output and do not require any collateral capacitors and diodes. The charge pump may be embodied in an MOS technology, nMOS, pMOS, or CMOS.
8 Citations
22 Claims
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1. A charge pump comprising:
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a plurality of stages including at least a first stage and a last stage, each of the stages comprising a first transistor having a first source terminal, a first drain terminal, a first gate terminal and a first body terminal;
a second transistor having a second source terminal, a second drain terminal, a second gate terminal, and a second body terminal;
wherein each transistor of each stage, except for the second transistor of the last stage, has its source and drain terminals connected to each other and to a body terminal of a next transistor;
wherein the first transistor of each stage has a first gate terminal connected to an alternating polarity voltage source and the second transistor of each stage has a second gate terminal connected to ground; and
wherein the first transistor of the first stage has a first body terminal connected to ground; and
the second transistor of the last stage has a second source terminal and a second drain terminal connected to an output terminal of the charge pump. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for making a charge pump comprising the steps of:
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providing at least one stage comprising a first transistor having a first source terminal, a first drain terminal, a first gate terminal and a first body terminal;
a second transistor having a second source terminal, a second drain terminal, a second gate terminal, and a second body terminal;
connecting the source and drain terminals of each transistor of each stage, with the exception of the source and drain terminals of the second transistor of a last stage, to each other and to a body terminal of a next transistor;
connecting a gate terminal of the first transistor of each stage to an alternating polarity voltage source;
connecting a gate terminal of a second transistor of each stage to ground;
connecting the body terminal of the first transistor of a first stage to ground; and
connecting the second source terminal and the second drain terminal of the second transistor of the last stage to an output terminal of the charge pump. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A passive change pump comprising:
an even-numbered sequence of transistors, each transistor in the sequence other than the last transistor having a source and drain connected to a body terminal of a next transistor in the sequence, the gate of each odd-numbered transistor in the sequence being connectable to an alternating polarity voltage source, and the gate of each even-numbered transistor in the sequence being coupled to a neutral terminal of the alternating polarity voltage source. - View Dependent Claims (22)
Specification