Amplifying circuit with adjustable amplification and transmitter system comprising such an amplifying circuit

• US 20050174175A1
• Filed: 01/10/2005
• Published: 08/11/2005
• Est. Priority Date: 07/10/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Heigelmayer, Bernhard, Pretl, Harald
• Granted Patent: US 7,109,796 B2
• Time in Patent Office: Days
• US Class Current: 330/254
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45244 the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
• CPC Class Codes: H03F 2203/45268 A common gate stage being coupled at the one or more outputs of the dif amp
• CPC Class Codes: H03F 2203/45541 the IC comprising dynamic biasing means, i.e. controlled by the input signal
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45564 the IC comprising one or more extra current sources
• CPC Class Codes: H03F 2203/45618 the IC comprising only one switch
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/7203 the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias current in the amplifier
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

The invention is directed to an amplifier circuit with adjustable gain which includes a plurality of parallel-connected differential amplifiers connected to a common cascode stage. An actuation unit is used to activate the differential amplifiers independently of one another on the basis of an applied control signal. The principle described makes it possible to dispense with inductances in the differential amplifier and hence to reduce unwanted crosstalk, while having a high linearity. Secondly, the amplifier'"'"'s drawn current matches the respective output power which can be tapped off. Overall, the principle described is particularly suitable for use in UMTS mobile radios.

Claims

1. An amplifier circuit with adjustable gain, comprising:

an input terminal pair configured to receive a differential input signal;

an output configured to output an amplified version of the differential input signal;

a control input configured to supply a gain factor to the amplifier circuit;

a cascode stage connected to the output and comprising two cascode transistors coupled together at a control terminal thereof;

a plurality of differential amplifiers connected together in parallel, each comprising a respective differential input connected to the input terminal pair, a respective differential output connected to the cascode stage, and a respective activation input, and wherein each differential amplifier further comprises two differential amplifier transistors coupled to a current mirror transistor, and wherein the current mirror transistor is coupled to the activation input and, together with the differential amplifier transistors, is configured to supply a reference current based on a signal at the activation input; and

an actuation unit comprising an input connected to the control input of the amplifier circuit, and a plurality of outputs, a respective one of which is connected to the activation input of a respective differential amplifier, and configured to selectively activate one or more differential amplifiers based on the gain factor supplied at the control input.

2. The amplifier circuit as claimed in claim 1, wherein the respective two differential amplifier transistors in the differential amplifiers each comprise a signal input terminal and a controlled section, and wherein the signal input terminals of the differential amplifiers are coupled to the input terminal pair of the amplifier circuit, and the controlled sections each couple an associated cascode transistor of the cascode stage to a reference potential connection.

3. The amplifier circuit of claim 1, wherein the differential amplifier transistors comprise field effect transistors, and the cascode transistors of the cascode stage comprise bipolar transistors.

4. The amplifier circuit of claim 1, wherein the actuation unit comprises a plurality of comparators, a respective one of which comprises an output connected to the activation input of an associated differential amplifier, the comparators each comprising a first input coupled to the control input of the amplifier circuit, and a second input configured to supply a respective, graduated threshold value.

5. The amplifier circuit of claim 4, further comprising a divider chain comprising a plurality of exponentially graduated tap nodes, a respective one of which is connected to a second input on an associated comparator in order to provide exponentially graduated threshold values.

6. The amplifier circuit of claim 4, wherein the comparators each comprise a differential amplifier with two differential transistors having control input terminals that form the inputs of the comparator, and wherein the output of the comparator is coupled to one of the two differential transistors via a current mirror.

7. The amplifier circuit of claim 6, wherein the differential transistors of the comparators comprise bipolar transistors.

8. An amplifier circuit, comprising:

a plurality of differential amplifier circuits coupled together in parallel between a differential signal input and a differential signal output, wherein each of the differential amplifier circuits comprises an activation input, and wherein each of the differential amplifier circuits is configured to be individually activated or deactivated based on a state of an activation signal thereat;

a cascode stage output circuit having a differential input coupled to the differential signal output, and a differential output forming an output of the amplifier circuit; and

an actuation unit having a control input configured to receive a control input signal indicative of a gain of the amplifier circuit, and a plurality of activation outputs respectively coupled to the activation inputs of the differential amplifier circuits, wherein the actuation unit is configured to activate a selected one or more differential amplifier circuits via a state of the activation outputs based on the control input signal and a predetermined allocation rule.

9. The amplifier circuit of claim 8, wherein each differential amplifier circuit comprises:

a differential transistor pair having control inputs coupled to the differential signal input, respectively; and

a current mirror transistor coupled to the differential transistor pair in a current mirror configuration, wherein a current input to the current mirror transistor via the activation input is mirrored to the differential transistor pair and provided at the differential signal output, respectively.

10. The amplifier circuit of claim 9, wherein the cascode stage output circuit comprises:

a first bipolar transistor having an emitter terminal coupled to one output of the differential signal output, a base terminal coupled to a bias potential, and a collector terminal forming one output of the amplifier circuit output; and

a second bipolar transistor having an emitter terminal coupled to another output of the differential signal output, a base terminal coupled to the bias potential, and a collector terminal forming another output of the amplifier circuit output.

11. The amplifier circuit of claim 8, wherein the actuation unit comprises:

a plurality of comparators, wherein each comparator comprises a first input coupled to the control input, a second input, and an output respectively forming one of the activation outputs of the actuation unit; and

a resistive chain coupled between two reference potentials, and forming a plurality of threshold voltage tap points thereacross, wherein each of the threshold voltage tap points is respectively coupled to the second input of the plurality of comparators,

wherein, based on the state of the control input signal, one or more of the comparators trigger based on their respective threshold voltage tap point, thereby selectively activating a corresponding one or more differential amplifier circuits.

12. The amplifier circuit of claim 11, wherein values of resistances along the resistive chain are exponentially weighted, thereby resulting in threshold voltage tap points that vary in a generally exponential manner.

13. The amplifier circuit of claim 8, wherein the differential input and differential output of the cascode stage output circuit comprises a low impedance differential input and a high impedance differential output, respectively.

14. A transmission arrangement, comprising:

a radio-frequency mixer configured to convert a baseband signal, which has been split into in-phase and quadrature components, to a radio frequency signal; and

an amplifier circuit, having an input terminal pair connected to an output of the radio-frequency mixer, and configured to amplify a radio-frequency signal at the output of the radio-frequency mixer using an adjustable gain factor, the amplifier circuit comprising;

a plurality of differential amplifier circuits coupled together in parallel between the input terminal pair and a differential signal output, wherein each of the differential amplifier circuits comprises an activation input, and wherein each of the differential amplifier circuits is configured to be individually activated or deactivated based on a state of an activation signal thereat;

a cascode stage output circuit having a differential input coupled to the differential signal output, and a differential output forming an output of the amplifier circuit; and

an actuation unit having a control input configured to receive a control input signal indicative of a gain of the amplifier circuit, and a plurality of activation outputs respectively coupled to the activation inputs of the differential amplifier circuits, wherein the actuation unit is configured to activate a selected one or more differential amplifier circuits via a state of the activation outputs based on the control input signal and a predetermined allocation rule.

15. The transmission arrangement of claim 14, wherein each differential amplifier circuit comprises:

a differential transistor pair having control inputs coupled to the input terminal pair, respectively; and

a current mirror transistor coupled to the differential transistor pair in a current mirror configuration, wherein a current input to the current mirror transistor via the activation input is mirrored to the differential transistor pair and provided at the differential signal output, respectively.

16. The transmission arrangement of claim 15, wherein the cascode stage output circuit comprises:

a first bipolar transistor having an emitter terminal coupled to one output of the differential signal output, a base terminal coupled to a bias potential, and a collector terminal forming one output of the amplifier circuit output; and

a second bipolar transistor having an emitter terminal coupled to another output of the differential signal output, a base terminal coupled to the bias potential, and a collector terminal forming another output of the amplifier circuit output.

17. The transmission arrangement of claim 14, wherein the actuation unit comprises:

a plurality of comparators, wherein each comparator comprises a first input coupled to the control input, a second input, and an output respectively forming one of the activation outputs of the actuation unit; and

a resistive chain coupled between two reference potentials, and forming a plurality of threshold voltage tap points thereacross, wherein each of the threshold voltage tap points is respectively coupled to the second input of the plurality of comparators,

wherein, based on the state of the control input signal, one or more of the comparators trigger based on their respective threshold voltage tap point, thereby selectively activating a corresponding one or more differential amplifier circuits.

18. The transmission arrangement of claim 17, wherein values of resistances along the resistive chain are exponentially weighted, thereby resulting in threshold voltage tap points that vary in a generally exponential manner.

19. The transmission arrangement of claim 14, wherein the differential input and differential output of the cascode stage output circuit comprises a low impedance differential input and a high impedance differential output, respectively.