Multi-bit-per-cell flash EEPROM memory with refresh

• US 20050174844A1
• Filed: 04/07/2005
• Published: 08/11/2005
• Est. Priority Date: 09/08/1997
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Hock C. So, Sau C. Wong
• Inventors: So, Hock C., Wong, Sau C.
• Granted Patent: US 7,170,781 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: B64C 27/006 Safety devices
• CPC Class Codes: G01N 29/14 using acoustic emission techniques echo of particles G01N29/046; measuring mechanical vibrations or acoustic waves in solids in general G01H1/00
• CPC Class Codes: G01N 29/227 related to high pressure, tension or stress conditions
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.

Claims

1. A non-volatile semiconductor memory comprising:

an array of memory cells;

drivers and decoders coupled to apply voltages to the array to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell;

an error detection circuit that detects errors in threshold voltages of memory cells storing data, wherein in response to detecting an error in the threshold voltage of memory cell, the error detection circuit signals for a refresh operation; and

a control circuit coupled to control the drivers and decoders, wherein during the refresh operation, the control circuit writes a corrected threshold voltage that corrects the error that the error detection circuit detected.

2-23. -23. (canceled)