Thin film transistor array panel for display
First Claim
1. A thin film transistor (TFT) array panel comprising:
- an insulating substrate;
a plurality of gate lines horizontally provided on the insulating substrate;
a plurality of data lines isolated from the gate line and intersecting the plurality of gate lines;
a plurality of pixel electrodes in pixel regions defined by intersecting the plurality of gate lines and the plurality of data lines;
a plurality of TFT for transmitting or intercepting an image signal transmitted through the plurality of data lines to the pixel electrodes in response to a scanning signal transmitted from the plurality of gate lines;
a transmission gate for distributing the image signal input from an input line to the plurality of data lines; and
a repair line intersecting the input line of the transmission gate.
2 Assignments
0 Petitions
Accused Products
Abstract
A TFT array panel is provided, including an insulating substrate, gate lines horizontally provided on the insulating substrate, data lines isolated from the gate lines and intersecting the gate lines, a pixel electrode in a pixel region defined by intersecting the gate lines and data lines, a TFT for transmitting or intercepting an image signal transmitted through the plurality of data lines to the pixel electrode in response to a scanning signal transmitted from the plurality of gate lines, a transmission gate for distributing the image signal input from an input line to the plurality of data lines, and a repair line intersecting the input line of the transmission gate. Therefore, since the input repair line and the input line of the transmission gate are intersected, a parasitic capacitance occurring between the repair line and the input line of the transmission gate can be reduced.
18 Citations
7 Claims
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1. A thin film transistor (TFT) array panel comprising:
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an insulating substrate;
a plurality of gate lines horizontally provided on the insulating substrate;
a plurality of data lines isolated from the gate line and intersecting the plurality of gate lines;
a plurality of pixel electrodes in pixel regions defined by intersecting the plurality of gate lines and the plurality of data lines;
a plurality of TFT for transmitting or intercepting an image signal transmitted through the plurality of data lines to the pixel electrodes in response to a scanning signal transmitted from the plurality of gate lines;
a transmission gate for distributing the image signal input from an input line to the plurality of data lines; and
a repair line intersecting the input line of the transmission gate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification