Multi-chassis broadcast router having a common clock

• US 20050175017A1
• Filed: 06/17/2003
• Published: 08/11/2005
• Est. Priority Date: 06/21/2002
• Status: Active Grant

• Current Assignee: Thomson Licensing (Vantiva SA)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Christensen, Carl L, Bytheway, David Lynn
• Granted Patent: US 7,167,479 B2
• Time in Patent Office: Days
• US Class Current: 370/396
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 45/28 using route fault recovery
• CPC Class Codes: H04L 45/583 Stackable routers
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04M 2201/14 Delay circuits; Timers
• CPC Class Codes: H04M 3/12 Marking faulty circuits "busy"; Enabling equipment to disengage itself from faulty circuits ; Using redundant circuits; Response of a circuit, apparatus or system to an error
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13167 Redundant apparatus
• CPC Class Codes: H04Q 2213/13214 Clock signals
• CPC Class Codes: H04Q 2213/13242 Broadcast, diffusion, multicast, point-to-multipoint (1 : N)
• CPC Class Codes: H04Q 2213/1334 Configuration within the switch
• CPC Class Codes: H04Q 2213/13341 Connections within the switch
• CPC Class Codes: H04Q 3/521 using semiconductors in the switching stages

Abstract

Supportably mounted by each chassis of a multi-chassis broadcast router are primary router matrix cards, redundant router matrix cards and clock-demanding input and output cards. A first master clock firesides on the primary router matrix card of a first chassis while a second master clock firesides on the redundant router matrix card of a second chassis. Each master clock is configured to provide a respective common clock signal to all of the input and output cards of the first and second chassis. Control logic determines whether the first master clock or the second master clock issues the common clock signal.

Claims

1. A multi-chassis broadcast router, comprising:

a first chassis in which a first routing engine and at least one clock-demanding component reside;

a second chassis in which a second routing engine and at least one clock-demanding component reside;

a first link coupling an input side of said first routing engine residing in said first chassis and an input side of said second routing engine residing in said second chassis; and

a master clock residing in said first chassis, said master clock coupled to said at least one clock-demanding component residing in said first chassis and to said at least one clock-demanding component residing in said second chassis via said first link, said master clock supplying said at least one clock-demanding component residing in said first chassis and said at least one clock-demanding component residing in said second chassis with a common clock signal.

2. The apparatus of claim 1, and further comprising:

a first router matrix card supportably mounted by said first chassis, said first routing engine and said master clock residing on said first router matrix card; and

wherein said at least one clock demanding component further comprises at least one input card and at least one output card.

3. The apparatus of claim 1, and further comprising:

a third chassis in which a third routing engine and at least one clock-demanding component reside;

a second link coupling said input side of said first routing engine residing in said first chassis and an input side of said third routing engine residing in said third chassis, said master clock residing in said first chassis coupled to said at least one clock-demanding component residing in said third chassis via said second link;

wherein said master clock residing in said first chassis supplies said at least one clock-demanding component residing in said third chassis with said common clock signal through.

4. The apparatus of claim 3, and further comprising:

a third link coupling said input side of said second routing engine residing in said second chassis and said input side of said third routing engine residing in said third chassis;

wherein said first routing engine residing in said first chassis, said second routing engine residing in said second chassis and said third routing engine residing in said third chassis are arranged in a fully connected topology.

5. The apparatus of claim 4, wherein a redundant routing engine resides in each one of said first, second and third chassis.

6. The apparatus of claim 5, and further comprising:

a fourth link coupling an input side of said redundant routing engine residing in said first chassis to an input side of said redundant routing engine residing in said second chassis;

a fifth link coupling said input side of said redundant routing engine residing in said first chassis to an input side of said redundant routing engine residing in said third chassis; and

a sixth link coupling said input side of said redundant routing engine residing in said second chassis to said input side of said redundant routing engine residing in said third chassis;

wherein said redundant routing engine residing in said first chassis, said redundant routing engine residing in said second chassis and said redundant routing engine residing in said third chassis are arranged in a second fully connected topology.

7. A multi-chassis broadcast router, comprising:

a first chassis, said first chassis supportably mounting a first router matrix card, a redundant router matrix card, at least one clock-demanding input card and at least one clock-demanding output card;

a second chassis, said first chassis supportably mounting a first router matrix card, a redundant router matrix card, at least one clock-demanding input card and at least one clock-demanding output card;

a first master clock residing on said first router matrix card supportably mounted within said first chassis, said first master clock coupled to said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said first chassis and to said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said second chassis, said first master clock supplying said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said first chassis and said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said second chassis with a common clock signal;

a second master clock residing on said redundant router matrix card supportably mounted within said second chassis, said second master clock coupled to said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said first chassis and to said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said second chassis, said second master clock supplying said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said first chassis and said at least one clock-demanding input card and said at least one clock-demanding output card supportably mounted by said second chassis with a redundant common clock signal; and

control logic coupled to said first master clock and said second master clock A, said control logic determining whether said first master clock should issue said common clock signal or whether said second master clock should issue said redundant common clock signal.

8. The apparatus of claim 7, wherein said control logic has a first input coupled to said first router matrix card supportably mounted by said first chassis and a second input coupled to said redundant router matrix supportably mounted by said second chassis, said control logic determining, based upon a first signal received via said first input and a second signal received via said second input whether said first master clock should issue said common clock signal or whether said second master clock should issue said redundant common clock signal.

9. The apparatus of claim 8, wherein:

a first routing engine and a first transmission expansion port reside on said first router matrix card supportably mounted by said first chassis; and

wherein;

a second routing engine and a second transmission expansion port reside on said redundant router matrix card supportably mounted by said second chassis.

10. The apparatus of claim 9, wherein:

said first input to said control logic is coupled to said first routing engine residing on said router matrix card supportably mounted by said first chassis and said second input to said control logic is coupled to said second routing engine residing on said redundant router matrix card supportably mounted by said second chassis; and

wherein

said control logic has a third input coupled to said transmission expansion port residing on said router matrix card supportably mounted by said first chassis and a fourth input coupled to said second transmission expansion port residing on said redundant router matrix card supportably mounted by said second chassis

said control logic determining, based upon said first signal received via said first input, said second signal received via said second input, a third signal received via said third input and a fourth signal received via said fourth input, whether said first master clock should issue said common clock signal or said second master clock should issue said redundant common clock signal.

11. The apparatus of claim 10, wherein said control logic further comprises:

a first state machine residing on said first router matrix card supportably mounted by said first chassis;

a second state machine residing on said redundant router matrix card supportably mounted by said second chassis;

said first state machine determining, based upon said first signal received via said first input, said second signal received via said second input, said third signal received via said third input and said fourth signal received via said fourth input, whether said first master clock should issue said common clock signal; and

said second state machine determining, based upon said first signal received via said first input, said second signal received via said second input, said third signal received via said third input and said fourth signal received via said fourth input, whether said second master clock should issue said redundant common clock signal;

wherein only one of said common clock signal and said redundant common clock signal can be issued at one time.