Equalizer status monitor

• US 20050175080A1
• Filed: 04/11/2003
• Published: 08/11/2005
• Est. Priority Date: 04/17/2002
• Status: Abandoned Application

• Current Assignee: Thomson Licensing SA (Vantiva SA)
• Original Assignee: Thomson Licensing SA (Vantiva SA)
• Inventors: Bouillett, Aaron Reel
• Application Number:
  US10/511,562
• Publication Number:
  US 20050175080A1
• Time in Patent Office: Days
• US Class Current: 375/229
• CPC Class Codes: H04L 2025/03382 Single of vestigal sideband
• CPC Class Codes: H04L 2025/037 Detection of convergence state
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03025 using a two-tap delay line
• CPC Class Codes: H04N 17/004 for digital television systems
• CPC Class Codes: H04N 5/211 Ghost signal cancellation H04N23/81 takes precedence

Abstract

A system for monitoring the output of an adaptive channel equalizer in order to determine if convergence has been achieved. A slicer samples data from the equalizer during a predetermined period. The output data from the slicer is forwarded to a microprocessor in order to apply a test standard to the slicer data. For example, if one of every possible transmitted symbol is detected by the microprocessor, convergence is assumed to have occurred. If the test criterion is not met, a reset signal is sent to the equalizer.

Claims

1. An apparatus for determining convergence of an equalizer, comprising:

an equalizer output signal;

a nearest element decision device, the nearest element decision device receiving the equalizer output signal and creating a decision device output signal containing permissible symbol values; and

a monitoring circuit, the monitoring circuit receiving the decision device output signal and applying a test criterion to data contained in the decision device output signal so as to determine equalizer convergence.

2. The apparatus of claim 1, wherein the equalizer is formed to include an infinite impulse response filter.

3. The apparatus of claim 1, wherein the nearest element decision device is a slicer.

4. The apparatus of claim 1, wherein the monitoring circuit receives the decision device output signal for a predetermined period of time representing an acquisition of a desired number of transmitted symbol values.

5. The apparatus of claim 4, further comprising a memory, the memory being coupled to the monitoring circuit and being adapted to store decision device output data and test criteria.

6. The apparatus of claim 5, wherein the test criteria for determining equalizer convergence includes identifying a desired sample of transmitted symbol values.

7. The apparatus of claim 6, wherein the desired sample of transmitted symbol values includes at least one of every possible symbol value.

8. The apparatus of claim 1, wherein the monitoring circuit is coupled to the equalizer, the monitoring circuit resetting the equalizer when the equalizer diverges.

9. The apparatus of claim 1, wherein the monitoring circuit is coupled to the equalizer, the monitoring circuit resetting the equalizer when the equalizer achieves an invalid state.

10. The apparatus of claim 1, wherein the equalizer output signal includes an image representative datastream containing data packets.

11. The apparatus of claim 1, wherein the monitoring circuit is a microprocessor.

12. An equalizer status monitoring device for use in a digital communication system, the device including an adaptive channel equalizer, a slicer and a monitoring circuit, wherein the digital communications system receives a vestigial sideband modulated signal containing high definition video information represented by a multiple level symbol constellation, the data having a data frame format constituted by a succession of data frames, the adaptive channel equalizer generating a first output signal which is input to the slicer, the slicer generating a second output signal which is input to the monitoring circuit, the monitoring circuit applying a test criteria to the second output signal to determine convergence of the adaptive channel equalizer.

13. The system of claim 12, wherein the monitoring circuit is coupled to the adaptive channel equalizer and resets the adaptive channel equalizer when the adaptive channel equalizer diverges.

14. The system of claim 12, wherein the monitoring circuit is coupled to the adaptive channel equalizer and resets the adaptive channel equalizer when the adaptive channel equalizer assumes an invalid state.

15. The system of claim 12, wherein the test criteria for determining convergence requires identifying at least some transmitted symbol values.

16. The system of claim 12, wherein the adaptive channel equalizer further comprises an infinite impulse response filter.

17. The system of claim 12, wherein the test criteria for determining convergence requires identifying at least one of each possible transmitted symbol value.

18. The system of claim 12 wherein the monitoring circuit is a microprocessor.

19. In a digital communications receiver including an adaptive equalization filter that desirably achieves a state of convergence and which undesirably achieves a state of divergence or an invalid state, a method of monitoring the state of the equalization filter comprising the steps of:

coupling an output signal from the equalization filter to a monitoring circuit;

causing the monitoring circuit to examine data contained within the output signal for a finite time period;

causing the monitoring circuit to apply a test protocol to the examined data; and

causing the monitoring circuit to reset the equalization filter when the test protocol detects a state of divergence.

20. A method according to claim 19, further comprising the step of causing the monitoring circuit to reset the equalization filter when the test protocol detects that the equalization filter has achieved an invalid state.

21. A method according to claim 19, further comprising the steps of:

coupling the equalization filter output signal to a slicer; and

coupling the slicer to the monitoring circuit such that the monitoring circuit examines data generated by the slicer.

22. A method according to claim 21, wherein the test protocol requires detection of each possible transmitted symbol value within the data generated by the slicer in order to find that the equalization filter has achieved a state of convergence.

23. The method of claim 19 wherein the monitoring circuit is a microprocessor.