METHODOF MAKING AN INTEGRATED CIRCUIT
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Accused Products
Abstract
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
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Citations
522 Claims
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1-155. -155. (canceled)
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156. A method of making an integrated circuit comprising:
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providing a substrate having a principal surface;
forming circuit devices on the principal surface; and
forming a stress-controlled dielectric membrane overlying the circuit devices. - View Dependent Claims (157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 207, 208, 215, 251, 252, 271, 272, 273, 394, 409, 410, 448, 449, 450, 451, 452)
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157. The method of claim 156, wherein the stress-controlled dielectric membrane comprises at least one or more stress-controlled dielectric layers.
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158. The method of claim 157, wherein the at least one or more stress-controlled dielectric layers are caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the at least one or more stress-controlled dielectric layers.
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159. The method of claim 158, wherein said stress is tensile.
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160. The method of claim 157, comprising forming at least one of the at least one stress-controlled dielectric layers by depositing one or more stress-controlled dielectric films.
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161. The method of claim 160, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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162. The method of claim 156, wherein the stress-controlled dielectric membrane is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric membrane.
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163. The method of claim 162, wherein said stress is tensile.
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164. The method of claim 156, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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165. The method of claim 156, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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166. The method of claim 165, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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167. The method of claim 156, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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168. The method of claim 167, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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207. The method of claim 156, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and
providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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208. The method of claim 156, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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215. The method of claim 157, wherein the at least one or more stress-controlled dielectric layers are caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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251. The method of claim 156, wherein the major portion of the substrate is removed prior to forming said circuitry.
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252. The method of claim 156, wherein the major portion of the substrate is removed after forming said circuitry.
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271. The method of claim 157, wherein the at least one or more stress-controlled dielectric layers are caused to be at least one of elastic and substantially flexible.
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272. The method of claim 157, wherein the at least one or more stress-controlled dielectric layers are caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the at least one or more stress-controlled dielectric layers.
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273. The method of claim 157, wherein the at least one or more stress-controlled dielectric layers are caused to be elastic and the at least one or more stress-controlled dielectric layers are caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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394. The method of claim 156, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuit devices, the principal surface overlying the barrier layer.
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409. The method of claim 157, wherein the stress-controlled dielectric layers are formed from at least one of an inorganic dielectric material and an organic dielectric material.
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410. The method of claim 409, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
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448. The method of claim 157, further comprising a plurality of interconnect conductors formed within at least one of the at least one or more stress-controlled dielectric layers, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
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449. The method of claim 156, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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450. The method of claim 156, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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451. The method of claim 157, wherein at least one of the at least one or more stress-controlled dielectric layers is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
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452. The method of claim 157, wherein at least one of the at least one or more stress-controlled dielectric layers is formed at a temperature of about 400°
- C.
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157. The method of claim 156, wherein the stress-controlled dielectric membrane comprises at least one or more stress-controlled dielectric layers.
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169. A method of making an integrated circuit comprising:
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providing a substrate having a principal surface;
forming circuit devices on the principal surface; and
forming a stress-controlled dielectric layer overlying the circuit devices. - View Dependent Claims (170, 171, 172, 173, 174, 175, 176, 177, 178, 216, 265, 266, 274, 275, 276, 395, 411, 412, 453, 454, 455, 456, 457)
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170. The method of claim 169, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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171. The method of claim 170, wherein said stress is tensile.
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172. The method of claim 169, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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173. The method of claim 172, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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174. The method of claim 169, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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175. The method of claim 169, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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176. The method of claim 175, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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177. The method of claim 169, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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178. The method of claim 177, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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216. The method of claim 169, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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265. The method of claim 169, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and
providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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266. The method of claim 169, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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274. The method of claim 169, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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275. The method of claim 169, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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276. The method of claim 169, wherein the stress-controlled dielectric layer is caused to be elastic and the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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395. The method of claim 169, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuit devices, the principal surface overlying the barrier layer.
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411. The method of claim 169, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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412. The method of claim 411, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
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453. The method of claim 169, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
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454. The method of claim 169, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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455. The method of claim 169, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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456. The method of claim 169, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
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457. The method of claim 169, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
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170. The method of claim 169, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
-
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179. A method of making an integrated circuit comprising:
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providing a substrate having a principal surface; and
forming circuitry on the principal surface of the substrate with a stress-controlled dielectric layer. - View Dependent Claims (180, 181, 182, 183, 184, 185, 186, 187, 188, 209, 210, 217, 277, 278, 279, 396, 413, 414, 458, 459, 460, 461, 462)
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180. The method of claim 179, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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181. The method of claim 180, wherein said stress is tensile.
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182. The method of claim 179, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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183. The method of claim 182, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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184. The method of claim 179, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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185. The method of claim 179, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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186. The method of claim 185, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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187. The method of claim 179, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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188. The method of claim 187, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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209. The method of claim 179, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and
providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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210. The method of claim 179, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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217. The method of claim 179, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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277. The method of claim 179, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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278. The method of claim 179, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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279. The method of claim 179, wherein the stress-controlled dielectric layer is caused to be elastic and the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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396. The method of claim 179, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry, the principal surface overlying the barrier layer.
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413. The method of claim 179, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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414. The method of claim 413, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
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458. The method of claim 179, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
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459. The method of claim 179, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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460. The method of claim 179, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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461. The method of claim 179, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
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462. The method of claim 179, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
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180. The method of claim 179, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
-
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189. A method of using an integrated circuit having a stress-controlled dielectric layer and interconnections formed passing through the stress-controlled dielectric layer, the method comprising:
transferring information through the interconnections formed passing through the stress-controlled dielectric layer. - View Dependent Claims (190, 191, 192, 193, 194, 195, 196, 197, 211, 212, 218, 280, 281, 282, 415, 416, 463, 464, 465, 466)
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190. The method of claim 189, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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191. The method of claim 190, wherein said stress is tensile.
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192. The method of claim 189, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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193. The method of claim 192, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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194. The method of claim 189, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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195. The method of claim 194, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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196. The method of claim 189, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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197. The method of claim 196, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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211. The method of claim 189, further comprising:
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providing a second integrated circuit overlying the integrated circuit; and
providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
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212. The method of claim 189, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
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218. The method of claim 189, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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280. The method of claim 189, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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281. The method of claim 189, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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282. The method of claim 189, wherein the stress-controlled dielectric layer is caused to be elastic and the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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415. The method of claim 189, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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416. The method of claim 415, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
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463. The method of claim 189, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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464. The method of claim 189, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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465. The method of claim 189, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
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466. The method of claim 189, wherein the stress-controlled dielectric layer is caused to have a withstand temperature of about 400°
- C. or less.
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190. The method of claim 189, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
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198. A method of using an integrated circuit having a data source formed on a first portion of the integrated circuit, a data sink formed on a second portion of the integrated circuit, interconnect circuitry interconnecting the data source and the data sink, the interconnect circuitry formed within a stress-controlled dielectric layer, the method comprising:
transferring a plurality of data bytes between the data source and data sink of the interconnect circuitry of the integrated circuit. - View Dependent Claims (199, 200, 201, 202, 203, 204, 205, 206, 213, 214, 219, 283, 284, 285, 417, 418, 467, 468, 469, 470)
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199. The method of claim 198, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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200. The method of claim 199, wherein said stress is tensile.
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201. The method of claim 198, further comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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202. The method of claim 201, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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203. The method of claim 198, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
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204. The method of claim 203, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
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205. The method of claim 198, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
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206. The method of claim 205, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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213. The method of claim 198, further comprising:
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a second integrated circuit overlying the integrated circuit; and
interconnect connecting portions of the circuitry of the second integrated circuit and the integrated circuit.
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214. The method of claim 198, further comprising:
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providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
-
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219. The method of claim 198, wherein the stress-controlled dielectric layer are caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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283. The method of claim 198, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
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284. The method of claim 198, wherein the stress-controlled dielectric layer is caused to be elastic and the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
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285. The method of claim 198, wherein the stress-controlled dielectric layer is caused to be elastic and the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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417. The method of claim 198, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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418. The method of claim 417, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
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467. The method of claim 198, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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468. The method of claim 198, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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469. The method of claim 198, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
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470. The method of claim 198, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
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199. The method of claim 198, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
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220. A method of making an integrated circuit comprising:
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forming on a substrate circuitry having active devices; and
forming a stress-controlled dielectric membrane overlying said active devices;
wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 256, 257, 262, 267, 268, 269, 270, 397, 419, 420, 471, 472, 473, 474, 475)
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221. The method of claim 220, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
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222. The method of claim 220, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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223. The method of claim 220, further comprising removing a major portion of the substrate.
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224. The method of claim 223, wherein the major portion of the substrate is removed prior to forming said circuitry.
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225. The method of claim 223, wherein the major portion of the substrate is removed after forming said circuitry.
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226. The method of claim 220, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
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227. The method of claim 220, wherein the stress-controlled dielectric membrane is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric membrane.
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228. The method of claim 227, wherein said stress is tensile.
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229. The method of claim 220, wherein the stress-controlled dielectric membrane comprises at least one or more stress-controlled dielectric layers.
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230. The method of claim 220, wherein the major portion of the substrate is removed prior to forming said circuitry.
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231. The method of claim 220, wherein the major portion of the substrate is removed after forming said circuitry.
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232. The method of claim 220, comprising forming the stress-controlled dielectric membrane by deposition of one or more stress-controlled dielectric films.
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233. The method of claim 232, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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256. The method of claim 220, further comprising:
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forming a second integrated circuit overlying the integrated circuit; and
forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
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257. The method of claim 220, further comprising:
-
forming a plurality of integrated circuits overlying the integrated circuit; and
forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
-
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262. The method of claim 229, wherein the at least one or more stress-controlled dielectric layers are caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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267. The method of claim 229, wherein the at least one or more stress-controlled dielectric layers are caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the at least one or more stress-controlled dielectric layers.
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268. The method of claim 229, wherein the at least one or more stress-controlled dielectric layers are caused to be at least one of elastic and substantially flexible.
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269. The method of claim 229, wherein the at least one or more stress-controlled dielectric layers are caused to be elastic and the at least one or more stress-controlled dielectric layers are caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the at least one or more stress-controlled dielectric layers.
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270. The method of claim 229, wherein the at least one or more stress-controlled dielectric layers are caused to be elastic and the at least one or more stress-controlled dielectric layers are caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
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397. The method of claim 220, further comprising:
-
providing a principal surface on the substrate; and
forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
-
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419. The method of claim 220, wherein the stress-controlled dielectric membrane is formed from at least one of an inorganic dielectric material and an organic dielectric material.
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420. The method of claim 419, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
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471. The method of claim 229, further comprising a plurality of interconnect conductors formed within at least one of the at least one or more stress-controlled dielectric layers, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
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472. The method of claim 220, further comprising at least one flexible integrated circuit overlying the integrated circuit.
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473. The method of claim 220, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
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474. The method of claim 229, wherein the at least one or more stress-controlled dielectric layers are capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
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475. The method of claim 229, wherein the at least one or more stress-controlled dielectric layers are formed at a temperature of about 400°
- C.
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221. The method of claim 220, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
-
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234. A method of making an integrated circuit comprising:
-
forming on a substrate circuitry having active devices; and
forming a stress-controlled dielectric layer overlying said active devices;
wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 258, 259, 263, 286, 287, 288, 398, 421, 422, 476, 477, 478, 479, 480)
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235. The method of claim 234, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
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236. The method of claim 234, comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
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237. The method of claim 236, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
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238. The method of claim 234, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
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239. The method of claim 234, further comprising removing a major portion of the substrate.
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240. The method of claim 239, wherein the major portion of the substrate is removed prior to forming said circuitry.
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241. The method of claim 239, wherein the major portion of the substrate is removed after forming said circuitry.
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242. The method of claim 234, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
243. The method of claim 234, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
244. The method of claim 243, wherein said stress is tensile.
-
258. The method of claim 234, further comprising:
-
forming a second integrated circuit overlying the integrated circuit; and
forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
259. The method of claim 234, further comprising:
-
forming a plurality of integrated circuits overlying the integrated circuit; and
forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
-
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263. The method of claim 234, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
286. The method of claim 234, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
-
287. The method of claim 234, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
288. The method of claim 234, wherein the stress-controlled dielectric layer is caused to be elastic and the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
398. The method of claim 234, further comprising:
- providing a principal surface on the substrate; and
forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
- providing a principal surface on the substrate; and
-
421. The method of claim 234, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
422. The method of claim 421, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
476. The method of claim 234, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
477. The method of claim 234, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
478. The method of claim 234, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
479. The method of claim 234, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
480. The method of claim 234, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
-
235. The method of claim 234, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
-
-
245. A method of making an integrated circuit comprising:
-
forming on a substrate circuitry having active devices;
forming a stress-controlled dielectric layer overlying said active devices; and
removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit. - View Dependent Claims (246, 247, 248, 249, 250, 253, 254, 255, 260, 261, 264, 289, 290, 291, 399, 423, 424, 481, 482, 483, 484, 485)
-
246. The method of claim 245, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
247. The method of claim 245, wherein the major portion of the substrate is removed after forming said circuitry.
-
248. The method of claim 245, comprising forming the stress-controlled dielectric layer by deposition of one or more stress-controlled dielectric films.
-
249. The method of claim 248, comprising depositing at least one of the one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
250. The method of claim 245, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
253. The method of claim 245, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
254. The method of claim 245, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
255. The method of claim 254, wherein said stress is tensile.
-
260. The method of claim 245, further comprising:
-
forming a second integrated circuit overlying the integrated circuit; and
forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
261. The method of claim 245, further comprising:
-
forming a plurality of integrated circuits overlying the integrated circuit; and
forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
-
-
264. The method of claim 245, wherein the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
289. The method of claim 245, wherein the stress-controlled dielectric layer is caused to be at least one of elastic and substantially flexible.
-
290. The method of claim 245, wherein the stress-controlled dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.
-
291. The method of claim 245, wherein stress-controlled dielectric layer is caused to be elastic and the stress-controlled dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
399. The method of claim 245, further comprising:
-
providing a principal surface on the substrate; and
forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
-
-
423. The method of claim 245, wherein the stress-controlled dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
424. The method of claim 423, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
481. The method of claim 245, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
482. The method of claim 245, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
483. The method of claim 245, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
484. The method of claim 245, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
485. The method of claim 245, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°
- C.
-
246. The method of claim 245, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
-
292. A method of making an integrated circuit comprising:
-
providing a substrate having a principal surface;
forming circuit devices on the principal surface; and
forming a low stress dielectric layer overlying the circuit devices. - View Dependent Claims (293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 400, 427, 428, 486, 487, 488, 489, 490)
-
293. The method of claim 292, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the low stress dielectric layer.
-
294. The method of claim 293, wherein said stress is tensile.
-
295. The method of claim 292, comprising forming the low stress dielectric layer by deposition of one or more low stress dielectric films.
-
296. The method of claim 295, comprising depositing at least one of the one or more of the low stress dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
297. The method of claim 292, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
298. The method of claim 292, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof.
-
299. The method of claim 292, further comprising removing a major portion of the substrate throughout a full extent thereof.
-
300. The method of claim 299, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
301. The method of claim 292, wherein the low stress dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
302. The method of claim 292, wherein the low stress dielectric layer is caused to be at least one of elastic and substantially flexible.
-
303. The method of claim 292, wherein the low stress dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to be at least one of elastic and substantially flexible.
-
304. The method of claim 292, wherein the low stress dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less and the low stress dielectric layer is caused to be at least one of elastic and substantially flexible.
-
305. The method of claim 292, further comprising:
-
providing a second integrated circuit overlying the integrated circuit; and
providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
306. The method of claim 292, further comprising:
-
providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
-
-
400. The method of claim 292, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuit devices, the principal surface overlying the barrier layer.
-
427. The method of claim 292, wherein the low stress dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
428. The method of claim 427, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
486. The method of claim 292, further comprising a plurality of interconnect conductors formed within the low stress dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
487. The method of claim 292, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
488. The method of claim 292, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
489. The method of claim 292, wherein the low stress dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
490. The method of claim 292, wherein the low stress dielectric layer is formed at a temperature of about 400°
- C.
-
293. The method of claim 292, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
-
-
307. A method of fabricating circuitry comprising the steps of:
-
providing a substrate having a principal surface;
forming circuit devices on the principal surface;
forming a low stress dielectric layer overlying the circuit devices; and
forming interconnections within the low stress dielectric layer between the circuit devices, wherein the interconnections are at least one of electrical and optical interconnections. - View Dependent Claims (308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 401, 429, 430, 491, 492, 493, 494)
-
308. The method of claim 307, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the low stress dielectric layer.
-
309. The method of claim 308, wherein said stress is tensile.
-
310. The method of claim 307, comprising forming the low stress dielectric layer by deposition of one or more low stress dielectric films.
-
311. The method of claim 310, comprising depositing at least one of the one or more of low stress dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
312. The method of claim 307, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
313. The method of claim 307, wherein the circuitry is able to be thinned to about 50 microns or less throughout a full extent thereof.
-
314. The method of claim 307, further comprising removing a major portion of the substrate throughout a full extent thereof.
-
315. The method of claim 314, wherein the circuitry is caused to have a thickness of about 50 microns or less.
-
316. The method of claim 307, wherein the low stress dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the circuitry is caused to have a thickness of about 50 microns or less.
-
317. The method of claim 307, wherein the low stress dielectric layer is caused to be at least one of elastic and substantially flexible.
-
318. The method of claim 307, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the low stress dielectric layer.
-
319. The method of claim 307, wherein the low stress dielectric layer is caused to be elastic and the low stress dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the circuitry is caused to have a thickness of about 50 microns or less.
-
320. The method of claim 307, further comprising:
-
providing a second circuitry overlying the circuitry; and
providing an interconnect that connects portions of the circuitry of the second circuitry and the circuitry.
-
-
321. The method of claim 307, further comprising:
-
providing a plurality of circuits overlying the circuitry; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of circuitry and the circuitry.
-
-
401. The method of claim 307, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuit devices, the principal surface overlying the barrier layer.
-
429. The method of claim 307, wherein the low stress dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
430. The method of claim 429, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
491. The method of claim 307, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
492. The method of claim 307, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
493. The method of claim 307, wherein the low stress dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
494. The method of claim 307, wherein the low stress dielectric layer is formed at a temperature of about 400°
- C.
-
308. The method of claim 307, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
-
-
322. A method of fabricating interconnect circuitry comprising the steps of:
-
providing a substrate having a principal surface;
forming a low stress dielectric layer overlying the principal surface; and
forming interconnections within the low stress dielectric layer, wherein the interconnections are at least one of electrical and optical interconnections. - View Dependent Claims (323, 324, 325, 326, 327, 328, 431, 432, 495, 496, 497, 498)
-
323. The method of claim 322, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the low stress dielectric layer.
-
324. The method of claim 323, wherein said stress is tensile.
-
325. The method of claim 322, comprising forming the low stress dielectric layer by deposition of one or more low stress dielectric films.
-
326. The method of claim 325, comprising depositing at least one of the one or more of low stress dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
327. The method of claim 322, wherein the low stress dielectric layer is caused to be at least one of elastic and substantially flexible.
-
328. The method of claim 322, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the low stress dielectric layer.
-
431. The method of claim 322, wherein the low stress dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
432. The method of claim 431, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
495. The method of claim 322, further comprising at least one flexible integrated circuit overlying the interconnect circuitry.
-
496. The method of claim 322, wherein the interconnect circuitry is capable of forming at least one of a substantially flexible interconnect circuitry and an elastic interconnect circuitry.
-
497. The method of claim 322, wherein the low stress dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
498. The method of claim 322, wherein the low stress dielectric layer is formed at a temperature of about 400°
- C.
-
323. The method of claim 322, wherein the low stress dielectric layer is caused to have a stress of at least one of about 8×
-
-
329. A method of making an integrated circuit comprising:
-
providing a substrate having a principal surface;
forming circuit devices on the principal surface; and
forming an elastic dielectric layer overlying the circuit devices. - View Dependent Claims (330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 402, 405, 406, 407, 408, 433, 434, 443, 499, 500, 501, 502, 503)
-
330. The method of claim 329, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer.
-
331. The method of claim 330, wherein said stress is tensile.
-
332. The method of claim 329, further comprising forming the elastic dielectric layer by deposition of one or more elastic dielectric films.
-
333. The method of claim 332, comprising depositing at least one of the one or more of the elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
334. The method of claim 329, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
335. The method of claim 329, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
-
336. The method of claim 335, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
-
337. The method of claim 329, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
-
338. The method of claim 337, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
339. The method of claim 329, wherein the elastic dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
340. The method of claim 329, further comprising:
-
providing a second integrated circuit overlying the integrated circuit; and
providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
341. The method of claim 329, further comprising:
-
providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
-
-
402. The method of claim 329, further comprising forming a barrier layer in the substrate parallel to the principal surface before forming the circuit devices, the principal surface overlying the barrier layer.
-
405. The method of claim 329, further comprising forming the elastic dielectric layer by deposition of one or more stress-controlled dielectric films.
-
406. The method of claim 405, wherein the stress-controlled dielectric films are caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric films.
-
407. The method of claim 406, wherein the stress is tensile.
-
408. The method of claim 405, further comprising depositing one or more of the stress-controlled dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
433. The method of claim 329, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
434. The method of claim 433, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
443. The method of claim 329, wherein the elastic dielectric layer is caused to be substantially flexible.
-
499. The method of claim 329, further comprising a plurality of interconnect conductors formed within the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
500. The method of claim 329, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
501. The method of claim 329, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
502. The method of claim 329, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
503. The method of claim 329, wherein the elastic dielectric layer is formed at a temperature of about 400°
- C.
-
330. The method of claim 329, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
-
-
342. A method of making an integrated circuit comprising:
-
forming on a substrate circuitry having active devices; and
forming an elastic dielectric layer overlying said active devices;
wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity. - View Dependent Claims (343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 403, 435, 436, 444, 504, 505, 506, 507, 508)
-
343. The method of claim 342, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer.
-
344. The method of claim 343, wherein said stress is tensile.
-
345. The method of claim 342, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.
-
346. The method of claim 342, comprising forming the elastic dielectric layer by deposition of one or more elastic dielectric films.
-
347. The method of claim 346, comprising depositing at least one of the one or more of the elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
348. The method of claim 342, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
349. The method of claim 342, further comprising removing a major portion of the substrate.
-
350. The method of claim 349, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
351. The method of claim 349, wherein the major portion of the substrate is removed after forming said circuitry.
-
352. The method of claim 342, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
353. The method of claim 342, wherein the elastic dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
354. The method of claim 342, further comprising:
-
forming a second integrated circuit overlying the integrated circuit; and
forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
355. The method of claim 342, further comprising:
-
forming a plurality of integrated circuits overlying the integrated circuit; and
forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
-
-
403. The method of claim 342, further comprising:
-
providing a principal surface on the substrate; and
forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
-
-
435. The method of claim 342, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
436. The method of claim 435, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
444. The method of claim 342, wherein the elastic dielectric layer is caused to be substantially flexible.
-
504. The method of claim 342, further comprising a plurality of interconnect conductors formed within the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
505. The method of claim 342, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
506. The method of claim 342, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
507. The method of claim 342, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
508. The method of claim 342, wherein the elastic dielectric layer is formed at a temperature of about 400°
- C.
-
343. The method of claim 342, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
-
-
356. A method of making an integrated circuit comprising:
-
forming on a substrate circuitry having active devices;
forming an elastic dielectric layer overlying said active devices; and
removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit. - View Dependent Claims (357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 404, 437, 438, 445, 509, 510, 511, 512, 513)
-
357. The method of claim 356, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer.
-
358. The method of claim 357, wherein said stress is tensile.
-
359. The method of claim 356, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
360. The method of claim 356, wherein the major portion of the substrate is removed after forming said circuitry.
-
361. The method of claim 356, comprising forming the elastic dielectric layer by deposition of one or more elastic dielectric films.
-
362. The method of claim 361, comprising depositing at least one of the one or more of the elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
363. The method of claim 356, wherein said substrate is at least one of a semiconductor substrate, a silicon wafer, and a dielectric substrate.
-
364. The method of claim 356, wherein the major portion of the substrate is removed prior to forming said circuitry.
-
365. The method of claim 356, wherein the major portion of the substrate is removed after forming said circuitry.
-
366. The method of claim 356, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
367. The method of claim 356, further comprising:
-
forming a second integrated circuit overlying the integrated circuit; and
forming an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
368. The method of claim 356, further comprising:
-
forming a plurality of integrated circuits overlying the integrated circuit; and
forming at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuit and the integrated circuit.
-
-
369. The method of claim 356, wherein the elastic dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
404. The method of claim 356, further comprising:
-
providing a principal surface on the substrate; and
forming a barrier layer in the substrate parallel to the principal surface before forming the circuitry having active devices, the principal surface overlying the barrier layer.
-
-
437. The method of claim 356, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
438. The method of claim 437, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
445. The method of claim 356, wherein the elastic dielectric layer is caused to be substantially flexible.
-
509. The method of claim 356, further comprising a plurality of interconnect conductors formed within the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
510. The method of claim 356, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
511. The method of claim 356, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
512. The method of claim 356, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
513. The method of claim 356, wherein the elastic dielectric layer is formed at a temperature of about 400°
- C.
-
357. The method of claim 356, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
-
-
370. A method of using an integrated circuit having an elastic dielectric layer and interconnections formed within and passing through the elastic dielectric layer, the method comprising:
transferring information through the interconnections formed passing through the elastic dielectric layer, wherein the interconnections are at least one of electrical and optical interconnections. - View Dependent Claims (371, 372, 373, 374, 375, 376, 377, 378, 379, 380, 381, 439, 440, 446, 514, 515, 516, 517)
-
371. The method of claim 370, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer.
-
372. The method of claim 371, wherein said stress is tensile.
-
373. The method of claim 370, further comprising forming the elastic dielectric layer by deposition of one or more elastic dielectric films.
-
374. The method of claim 373, comprising depositing at least one of the one or more of the elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
375. The method of claim 370, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
-
376. The method of claim 375, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
-
377. The method of claim 370, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
-
378. The method of claim 377, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
379. The method of claim 370, wherein the elastic dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
380. The method of claim 370, further comprising:
-
providing a second integrated circuit overlying the integrated circuit; and
providing an interconnect that connects portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
381. The method of claim 370, further comprising:
-
providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
-
-
439. The method of claim 370, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
440. The method of claim 439, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
446. The method of claim 370, wherein the elastic dielectric layer is caused to be substantially flexible.
-
514. The method of claim 370, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
515. The method of claim 370, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
516. The method of claim 370, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
517. The method of claim 370, wherein the elastic dielectric layer is caused to have a withstand temperature of about 400°
- C. or less.
-
371. The method of claim 370, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
-
382. A method of using an integrated circuit having a data source formed on a first portion of the integrated circuit, a data sink formed on a second portion of the integrated circuit, interconnect circuitry interconnecting the data source and the data sink, the interconnect circuitry formed within an elastic dielectric layer, the method comprising:
transferring a plurality of data bytes between the data source and data sink of the interconnect circuitry of the integrated circuit. - View Dependent Claims (383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 441, 442, 447, 518, 519, 520, 521, 522)
-
383. The method of claim 382, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
- 108 dynes/cm2 or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer.
-
384. The method of claim 383, wherein said stress is tensile.
-
385. The method of claim 382, further comprising forming the elastic dielectric layer by deposition of one or more elastic dielectric films.
-
386. The method of claim 385, comprising depositing at least one of the one or more of the elastic dielectric films using at least one of multiple RF energy sources, Chemical Vapor Deposition, and Plasma Enhanced Chemical Vapor Deposition.
-
387. The method of claim 382, wherein the integrated circuit is able to have a major portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.
-
388. The method of claim 387, wherein the integrated circuit is able to be thinned to about 50 microns or less throughout a full extent thereof while retaining its structural integrity.
-
389. The method of claim 382, further comprising removing a major portion of the substrate throughout a full extent thereof without impairing the structural integrity of the integrated circuit.
-
390. The method of claim 389, wherein the integrated circuit is caused to have a thickness of about 50 microns or less.
-
391. The method of claim 382, wherein the elastic dielectric layer is caused to have a stress of about 8×
- 108 dynes/cm2 or less and the integrated circuit is caused to have a thickness of about 50 microns or less.
-
392. The method of claim 382, further comprising:
-
a second integrated circuit overlying the integrated circuit; and
interconnect connecting portions of the circuitry of the second integrated circuit and the integrated circuit.
-
-
393. The method of claim 382, further comprising:
-
providing a plurality of integrated circuits overlying the integrated circuit; and
providing at least one interconnect that connects portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.
-
-
441. The method of claim 382, wherein the elastic dielectric layer is formed from at least one of an inorganic dielectric material and an organic dielectric material.
-
442. The method of claim 441, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.
-
447. The method of claim 382, wherein the elastic dielectric layer is caused to be substantially flexible.
-
518. The method of claim 382, further comprising a plurality of interconnect conductors formed within the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.
-
519. The method of claim 382, further comprising at least one flexible integrated circuit overlying the integrated circuit.
-
520. The method of claim 382, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.
-
521. The method of claim 382, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.
-
522. The method of claim 382, wherein the elastic dielectric layer is caused to have a withstand temperature of about 400°
- C. or less.
-
383. The method of claim 382, wherein the elastic dielectric layer is caused to have a stress of at least one of about 8×
-
425. (canceled)
-
426. (canceled)
Specification
- Resources
-
Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
-
Original AssigneeELM TECHNOLOGY CORPORATION
-
InventorsLeedy, Glenn J.
-
Granted Patent
-
Time in Patent OfficeDays
-
Field of Search
-
US Class Current438/107
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CPC Class CodesG02F 1/13452 Conductors connecting drive...G02F 1/136281 having a transmissive semic...G03F 7/70658 Electrical testingG11C 29/006 at wafer scale level, i.e. ...H01L 21/762 Dielectric regions , e.g. E...H01L 21/76264 SOI together with lateral i...H01L 21/76289 Lateral isolation by air gapH01L 21/764 Air gaps H01L21/76264 takes...H01L 21/8221 Three dimensional integrate...H01L 2224/0401 Bonding areas specifically ...H01L 2224/05552 in top viewH01L 2224/0557 the external layer being di...H01L 2224/13009 Bump connector integrally f...H01L 2224/16225 the item being non-metallic...H01L 2224/16227 the bump connector connecti...H01L 2224/80001 by connecting a bonding are...H01L 23/538 the interconnection structu...H01L 23/5381 Crossover interconnections,...H01L 23/5383 Multilayer substrates H01L2...H01L 23/5386 Geometry or layout of the i...H01L 23/5387 : Flexible insulating substra...H01L 25/0652 : the devices being arranged ...H01L 25/0655 : the devices being arranged ...H01L 25/50 : Multistep manufacturing pro...H01L 27/0207 : Geometrical layout of the c...H01L 2924/00 : Indexing scheme for arrange...H01L 2924/00011 : Not relevant to the scope o...H01L 2924/0002 : Not covered by any one of g...H01L 2924/01014 : Silicon [Si]H01L 2924/01019 : Potassium [K]H01L 2924/0102 : Calcium [Ca]H01L 2924/01057 : Lanthanum [La]H01L 2924/01078 : Platinum [Pt]H01L 2924/01079 : Gold [Au]H01L 2924/1305 : Bipolar Junction Transistor...H01L 2924/13091 : Metal-Oxide-Semiconductor F...H01L 2924/14 : Integrated circuitsH01L 2924/15153 : the die mounting substrate ...H01L 2924/15165 : Monolayer substrateH01L 2924/15312 : being a pin array, e.g. PGAH01L 2924/3011 : ImpedanceH01L 2924/3025 : Electromagnetic shieldingY10S 148/135 : Removal of substrateY10S 438/928 : Front and rear surface proc...Y10S 438/938 : Lattice strain control or u...Y10S 438/942 : MaskingY10S 438/967 : Semiconductor on specified ...Y10S 438/977 : Thinning or removal of subs...Y10T 29/49128 : Assembling formed circuit t...Y10T 29/49162 : by using wire as conductive...Y10T 29/49165 : by forming conductive walle...Y10T 29/49171 : with encapsulatingY10T 29/4921 : with bonding