Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods

• US 20050176222A1
• Filed: 05/08/2003
• Published: 08/11/2005
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ogura, Atsushi
• Granted Patent: US 7,605,443 B2
• Time in Patent Office: Days
• US Class Current: 438/514
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The present invention relates to a method of manufacturing a semiconductor substrate, which enables a semiconductor device to have high speed operating characteristics and high performance characteristics such as lower electrical power consumption, and a method of manufacturing a semiconductor device including a method of manufacturing the semiconductor substrate thereof in a process, as well as to a semiconductor substrate manufactured by the method of manufacturing the same and a semiconductor device manufactured using the semiconductor substrate.

Claims

1. A method of manufacturing a semiconductor substrate, comprising:

a first step of selectively implanting ions into a predetermined region in a substrate, the implanted ions, in turn, forming a plurality of micro-cavities in said predetermined region; and

a second step of giving heat treatment to the substrate, thereby, after discharge of said implanted ions outside of said substrate as gas, allowing growth of said plurality of respective micro-cavities and further combination of adjacent micro-cavities with each other to form an embedded insulating region comprising a combined cavity present all over said predetermined region.

2. The method of manufacturing a semiconductor substrate according to claim 1, wherein said combined cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface.

3. The method of manufacturing a semiconductor substrate according to claim 1, wherein heat treatment in said second step allows said substrate to be softened due to inclusion of high-temperature heat treatment carried out in a high temperature range of not less than 1000°

C., and

even if a surface of a substrate corresponding to a region in which said cavity is formed is elevated, in a moment when said cavity is formed within said substrate, allows the surface of the substrate to be returned to flatness at once, so that a surface of said substrate which is finally obtained is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate.

4. The method of manufacturing a semiconductor substrate according to claim 1, wherein heat treatment in said second step includes high-temperature heat treatment, and the high-temperature heat treatment allowing adjacent micro-cavities to be combined with each other to form a combined cavity present all over said predetermined region.

5. The method of manufacturing a semiconductor substrate according to claim 4, wherein said high-temperature heat treatment is carried out in a high-temperature range of not less than 1000°

C.

6. The method of manufacturing a semiconductor substrate according to claim 5, wherein in said second step, a process of discharging said implanted ions outside of said substrate as gas comprises low-temperature heat treatment carried out in a low-temperature range of not less than 400°

C. through less than 700°

C., before said high-temperature heat treatment.

7. The method of manufacturing a semiconductor substrate according to claim 5, wherein said second step further includes middle-temperature heat treatment carried out in a middle-temperature region of not less than 700°

C. through less than 1000°

C. in order to allow growth of said plurality of respective micro-cavities.

8. The method of manufacturing a semiconductor substrate according to claim 5, wherein said second step further includes low-temperature heat treatment carried out in a low-temperature region of not less than 400°

C. through less than 700°

C. in order to discharge said implanted ions outside of said substrate as gas, and middle-temperature heat treatment carried out in a middle-temperature region of not less than 700°

C. through less than 1000°

C. in order to allow growth of said plurality of respective micro-cavities, before said high-temperature heat treatment.

9. The method of manufacturing a semiconductor substrate according to claim 8, wherein said low-temperature heat treatment is carried out at not less than 400°

C. through less than 600°

C., said middle-temperature heat treatment is carried out at not less than 800°

C. through less than 1000°

C., and said high-temperature heat treatment is carried out at a temperature increased further from 1200°

C.

10. The method of manufacturing a semiconductor substrate according to claim 4, wherein in said second step, an oxide film at least coating an inside surface which completely closes said inner space of said cavity is formed by carrying out at least said high-temperature heat treatment in oxygen rich atmosphere.

11. The method of manufacturing a semiconductor substrate according to claim 10, wherein said oxide film has a thicker film thickness in a portion, which is formed on side walls of said cavity than in a portion, which is formed on inside upper and lower surfaces of said cavity.

12. The method of manufacturing a semiconductor substrate according to claim 11, wherein said oxide film not only coats an inside surface of said cavity, but also includes at least one columnar portion which is formed in inner space of said cavity.

13. The method of manufacturing a semiconductor substrate according to claim 11, wherein said oxide film not only coats an inside surface of said cavity, but also includes at least one barrier-structure portion which is formed in inner space of said cavity.

14. The method of manufacturing a semiconductor substrate according to claim 10, wherein said high-temperature heat treatment is carried out in said oxygen rich atmosphere until said oxide film fills up inner space of said cavity.

15. The method of manufacturing a semiconductor substrate according to claim 10, wherein oxygen rich atmosphere is utilized only during the last certain period of time of a period in which said high-temperature heat treatment is carried out.

16. The method of manufacturing a semiconductor substrate according to claim 10, wherein said second step further includes a process of removing a surface oxide film formed on a surface of said substrate after said high-temperature heat treatment by carrying out said high-temperature heat treatment in said oxygen rich atmosphere.

17. The method of manufacturing a semiconductor substrate according to claim 10, comprising a process of forming an oxide film coating an inner surface of said cavity, then, further forming at least one communication hole for communicating said cavity with outside of said substrate on said substrate, and forming at least one insulating film different from an oxide film on a surface of said oxide film through the at least one communication hole.

18. The method of manufacturing a semiconductor substrate according to claim 4, wherein after said cavity is formed, at least one communication hole for communicating said cavity with outside of said substrate is further formed on said substrate to form an insulating film comprising at least one layer structure coating at least an inside surface of said cavity through the at least one communication hole.

19. The method of manufacturing a semiconductor substrate according to claim 1, wherein said ions are at least one ion selected from the group consisting of hydrogen ion, helium ion, neon ion, and fluorine ion.

20. The method of manufacturing a semiconductor substrate according to claim 19, wherein in said first step, said ion implantation is carried out at room temperature.

21. The method of manufacturing a semiconductor substrate according to claim 19, wherein in said first step, said ion implantation is carried out at a temperature higher than room temperature.

22. The method of manufacturing a semiconductor substrate according to claim 1, wherein in said first step, a mask exclusively for ion implantation is used to selectively implant said ions only into a predetermined region of said substrate.

23. The method of manufacturing a semiconductor substrate according to claim 1, wherein in said first step, at least one electrode is formed on said substrate, and said at least one electrode being used as a mask to selectively implant said ions only into a predetermined region of said substrate, whereby in said second step, said cavity self-aligning to said at least one electrode is formed.

24. The method of manufacturing a semiconductor substrate according to claim 1, wherein in said first step, at least one isolation region is formed on an upper portion region of said substrate, and said at least one isolation region being used as a mask to selectively implant said ions only into a predetermined region of said substrate, whereby in said second step, said cavity self-aligning to said at least one isolation region is formed.

25. The method of manufacturing a semiconductor substrate according to claim 1, wherein said predetermined region extends over a single semiconductor device element forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said semiconductor device element forming region.

26. The method of manufacturing a semiconductor substrate according to claim 1, wherein said predetermined region extends over a single circuit block forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said circuit block forming region.

27. The method of manufacturing a semiconductor substrate according to claim 1, wherein said semiconductor substrate is a silicon substrate.

28. The method of manufacturing a semiconductor substrate according to claim 1, further comprising a process of forming at least one single crystal semiconductor layer on said substrate surface, after said second step.

29. A method of manufacturing a semiconductor substrate, comprising:

a first step of selectively implanting ions into a predetermined region in a substrate, the implanted ions, in turn, forming a plurality of micro-cavities in said predetermined region; and

a second step of giving heat treatment to said substrate, thereby, after discharge of said implanted ions outside of said substrate as gas, allowing growth of said plurality of respective micro-cavities and further combination of adjacent micro-cavities with each other to form an embedded insulating region comprising a combined cavity present all over said predetermined region,

wherein said combined cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface,

wherein heat treatment in said second step includes high-temperature heat treatment, said high-temperature heat treatment allowing combination of adjacent micro-cavities with each other to form said combined cavity present all over said predetermined region, and

wherein an oxide film at least coating said inside surface of said cavity is formed by carrying out said high-temperature heat treatment in oxygen rich atmosphere, during at least the last certain period of time of said high-temperature heat treatment.

30. The method of manufacturing a semiconductor substrate according to claim 29, wherein heat treatment in said second step allows said substrate to be softened due to inclusion of high-temperature heat treatment carried out in a high temperature range of not less than 1000°

C., and

even if a surface of a substrate corresponding to a region in which said cavity is formed is elevated, in a moment when said cavity is formed within said substrate, allows the surface of the substrate to be returned to flatness at once, so that a surface of said substrate which is finally obtained is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate.

31. The method of manufacturing a semiconductor substrate according to claim 29, wherein said high-temperature heat treatment is carried out in a high-temperature range of not less than 1000°

C.

32. The method of manufacturing a semiconductor substrate according to claim 31, wherein in said second step, a process of discharging said implanted ions outside of said substrate as gas comprises low-temperature heat treatment carried out in a low-temperature region of not less than 400°

C. through less than 700°

C., before said high-temperature heat treatment.

33. The method of manufacturing a semiconductor substrate according to claim 31, wherein said second step further includes middle-temperature heat treatment carried out in a middle-temperature region of not less than 700°

C. through less than 1000°

C. in order to allow growth of said plurality of respective micro-cavities, before said high-temperature heat treatment.

34. The method of manufacturing a semiconductor substrate according to claim 31, wherein said second step further includes low-temperature heat treatment carried out in a low-temperature region of not less than 400°

C. through less than 700°

C. in order to discharge said implanted ions outside of said substrate as gas, and middle-temperature heat treatment carried out in a middle-temperature region of not less than 700°

C. through less than 1000°

C. in order to allow growth of said plurality of respective micro-cavities, before said high-temperature heat treatment.

35. The method of manufacturing a semiconductor substrate according to claim 34, wherein said low-temperature heat treatment is carried out at not less than 400°

C. through less than 600°

C., said middle-temperature heat treatment is carried out at not less than 800°

C. through less than 1000°

C., and said high-temperature heat treatment is carried out at a temperature increased further from 1200°

C.

36. The method of manufacturing a semiconductor substrate according to claim 29, wherein said oxide film has a thicker film thickness in a portion, which is formed on side walls of said cavity than in a portion, which is formed on inside upper and lower surfaces of said cavity.

37. The method of manufacturing a semiconductor substrate according to claim 36, wherein said oxide film not only coats an inside surface of said cavity, but also includes at least one columnar portion which is formed in inner space of said cavity.

38. The method of manufacturing a semiconductor substrate according to claim 36, wherein said oxide film not only coats an inside surface of said cavity, but also includes at least one barrier-structure portion which is formed in inner space of said cavity.

39. The method of manufacturing a semiconductor substrate according to claim 29, wherein said high-temperature heat treatment is carried out in said oxygen rich atmosphere until said oxide film fills up inner space of said cavity.

40. The method of manufacturing a semiconductor substrate according to claim 29, wherein oxygen rich atmosphere is utilized only during, the last certain period of time of a period in which said high-temperature heat treatment is carried out.

41. The method of manufacturing a semiconductor substrate according to claim 29, further comprising a process of removing a surface oxide film formed on a surface of said substrate by said high-temperature heat treatment carried out in said oxygen rich atmosphere, after said high-temperature heat treatment.

42. The method of manufacturing a semiconductor substrate according to claim 29, wherein said ions are at least one ion selected from the group consisting of hydrogen ion, helium ion, neon ion, and fluorine ion.

43. The method of manufacturing a semiconductor substrate according to claim 42, wherein in said first step, said ion implantation is carried out at room temperature.

44. The method of manufacturing a semiconductor substrate according to claim 42, wherein in said first step, said ion implantation is carried out at a temperature higher than room temperature.

45. The method of manufacturing a semiconductor substrate according to claim 29, wherein in said first step, a mask exclusively for ion implantation is used to selectively implant said ions only into a predetermined region of said substrate.

46. The method of manufacturing a semiconductor substrate according to claim 29, wherein in said first step, at least one electrode is formed on said substrate, said at least one electrode being used as a mask to selectively implant said ions only into a predetermined region of said substrate, whereby in said second step, said cavity self-aligning to said at least one electrode is formed.

47. The method of manufacturing a semiconductor substrate according to claim 29, wherein in said first step, at least one isolation region is formed on an upper portion region of said substrate, said at least one isolation region being used as a mask to selectively implant said ions only into a predetermined region of said substrate, whereby in said second step, said cavity self-aligning to said at least one isolation region is formed.

48. The method of manufacturing a semiconductor substrate according to claim 29, wherein said predetermined region extends over a single semiconductor device element forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said semiconductor device element forming region.

49. The method of manufacturing a semiconductor substrate according to claim 29, wherein said predetermined region extends over a single circuit block forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said circuit block forming region.

50. The method of manufacturing a semiconductor substrate according to claim 29, wherein said semiconductor substrate is a silicon substrate.

51. The method of manufacturing a semiconductor substrate according to claim 29, further comprising a process of forming at least one single crystal semiconductor layer on said substrate surface after said second step.

52. A method of manufacturing a semiconductor substrate, comprising:

a first step of selectively implanting ions into a predetermined region in a substrate, the implanted ions, in turn, forming a plurality of micro-cavities in said predetermined region; and

a second step of giving heat treatment to the substrate, thereby, after discharge of said implanted ions outside of said substrate as gas, allowing growth of said plurality of respective micro-cavities and further combination of adjacent micro-cavities with each other to form an embedded insulating region comprising a combined cavity present all over said predetermined region,

wherein said combined cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface,

wherein heat treatment in said second step includes high-temperature heat treatment, said high-temperature heat treatment allowing combination of adjacent micro-cavities with each other to form said combined cavity present all over said predetermined region, and

wherein an oxide film filling up said inner space of said cavity is formed by carrying out said high-temperature heat treatment in oxygen rich atmosphere, during at least the last certain period of time of said high-temperature heat treatment.

53. The method of manufacturing a semiconductor substrate according to claim 52, wherein heat treatment in said second step allows said substrate to be softened due to inclusion of high-temperature heat treatment carried out in a high temperature range of not less than 1000°

C., and

even if a surface of a substrate corresponding to a region in which said cavity is formed is elevated, in a moment when said cavity is formed within said substrate, allows the surface of the substrate to be returned to flatness at once, so that a surface of said substrate which is finally obtained is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate.

54. The method of manufacturing a semiconductor substrate according to claim 53, wherein in said second step, a process of discharging said implanted ions outside of said substrate as gas comprises low-temperature heat treatment carried out in a low-temperature region of not less than 400°

C. through less than 700°

C., before said high-temperature heat treatment.

55. The method of manufacturing a semiconductor substrate according to claim 53, wherein said second step further includes middle-temperature heat treatment carried out in a middle-temperature region of not less than 700°

C. through less than 1000°

C. in order to allow growth of said plurality of respective micro-cavities, before said high-temperature heat treatment.

56. The method of manufacturing a semiconductor substrate according to claim 53, wherein said second step further includes low-temperature heat treatment carried out in a low-temperature region of not less than 400°

C. through less than 700°

C. in order to discharge said implanted ions outside of said substrate as gas, and middle-temperature heat treatment carried out in a middle-temperature region of not less than 700°

C. through less than 1000°

C. in order to allow growth of said plurality of respective micro-cavities, before said high-temperature heat treatment.

57. The method of manufacturing a semiconductor substrate according to claim 56, wherein said low-temperature heat treatment is carried out at not less than 400°

C. through less than 600°

C., said middle-temperature heat treatment is carried out at not less than 800°

C. through less than 1000°

C., and said high-temperature heat treatment is carried out at a temperature increased further from 1200°

C.

58. The method of manufacturing a semiconductor substrate according to claim 52, further comprising a process of removing a surface oxide film formed on a surface of said substrate by said high-temperature heat treatment carried out in said oxygen rich atmosphere, after said high-temperature heat treatment.

59. A method of manufacturing a semiconductor device, comprising:

a first step of selectively implanting ions into a predetermined region in a substrate, the implanted ions, in turn, forming a plurality of micro-cavities in said predetermined region;

a second step of giving heat treatment to said substrate, thereby, after discharge of said implanted ions outside of said substrate as gas, allowing growth of said plurality of respective micro-cavities and further combination of adjacent micro-cavities with each other to form an embedded insulating region comprising a combined cavity present all over said predetermined region; and

a third step of forming at least one semiconductor device element on a surface region of the substrate on said embedded insulating region.

60. The method of manufacturing a semiconductor device according to claim 59, wherein said combined cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface.

61. The method of manufacturing a semiconductor device according to claim 59,

wherein heat treatment in said second step allows said substrate to be softened due to inclusion of high-temperature heat treatment carried out in a high temperature range of not less than 1000°

C., and even if a surface of a substrate corresponding to a region in which said cavity is formed is elevated, in a moment when said cavity is formed within said substrate, allows the surface of the substrate to be returned to flatness at once, so that a surface of said substrate which is finally obtained is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate, and

wherein in said third step, said at least one semiconductor device element is formed on said flat substrate surface.

62. The method of manufacturing a semiconductor device according to claim 59, wherein in said second step, an oxide film at least coating an inside surface which completely closes said inner space of said cavity is formed by carrying out at least said high-temperature heat treatment in oxygen rich atmosphere.

63. The method of manufacturing a semiconductor device according to claim 62, wherein said oxide film has a thicker film thickness in a portion, which is formed on side walls of said cavity than in a portion, which is formed on inside upper and lower surfaces of said cavity.

64. The method of manufacturing a semiconductor device according to claim 63, wherein said oxide film not only coats an inside surface of said cavity, but also includes at least one columnar portion which is formed in inner space of said cavity.

65. The method of manufacturing a semiconductor device according to claim 63, wherein said oxide film not only coats an inside surface of said cavity, but also includes at least one barrier-structure portion which is formed in inner space of said cavity.

66. The method of manufacturing a semiconductor device according to claim 62, wherein said high-temperature heat treatment is carried out in said oxygen rich atmosphere until said oxide film fills up inner space of said cavity.

67. The method of manufacturing a semiconductor device according to claim 62,

wherein said second step further includes a process of removing a surface oxide film formed on a surface of said substrate by carrying out said high-temperature heat treatment in said oxygen rich atmosphere, after said high-temperature heat treatment, and

wherein in said third step, said at least one semiconductor device element is formed on a surface of said substrate after removal of the surface oxide film.

68. The method of manufacturing a semiconductor device according to claim 59,

wherein in said first step, at least one gate electrode structure is formed on said substrate, said at least one gate electrode being used as a mask to selectively implant said ions into said substrate,

wherein in said second step, said cavity self-aligning to said at least one gate electrode structure is formed, and

wherein in said third step, a source region and a drain region are formed in said substrate.

69. The method of manufacturing a semiconductor device according to claim 59,

wherein in said first step, at least one isolation region is formed on an upper portion region of said substrate, said at least one isolation region being used as a mask to selectively implant said ions into said substrate,

wherein in said second step, said cavity self-aligning to said at least one isolation region is formed, and

wherein in said third step, said at least one semiconductor device element is formed on a surface region of the substrate above said cavity.

70. The method of manufacturing a semiconductor device according to claim 59, wherein said predetermined region extends over a single semiconductor device element forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said semiconductor device element forming region.

71. The method of manufacturing a semiconductor device according to claim 59, wherein said predetermined region extends over a single circuit block forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said circuit block forming region.

72. The method of manufacturing a semiconductor device according to claim 59, wherein said semiconductor substrate is a silicon substrate.

73. The method of manufacturing a semiconductor device according to claim 59, further comprising a process of forming at least one single crystal semiconductor layer on said substrate surface after said second step, wherein in said third step, said at least one semiconductor device element is formed on said at least one single crystal semiconductor layer.

74. A semiconductor substrate comprising an embedded insulating region comprising a combined, flat-shaped cavity present all over a predetermined region in a substrate,

wherein said cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface, wherein said inside surface is coated with at least an oxide film, said oxide film having a thicker film thickness in a portion, which is formed on side walls of said cavity than in a portion, which is formed on inside upper and lower surfaces of said cavity.

75. The semiconductor substrate according to claim 74, wherein a surface of said substrate is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate.

77. The semiconductor substrate according to claim 74, wherein said oxide film not only coats said inside surface of said cavity, but also includes at least one columnar portion extending in inner space of said cavity.

78. The semiconductor substrate according to claim 74, wherein said oxide film not only coats said inside surface of said cavity, but also includes at least one barrier-structure portion extending in inner space of said cavity.

80. The semiconductor substrate according to claim 74,

wherein said cavity self-aligns to at least one electrode present on said substrate.

81. The semiconductor substrate according to claim 74,

wherein said cavity self-aligns to at least one isolation region present on said substrate.

82. The semiconductor substrate according to claim 74,

wherein said predetermined region extends over a single semiconductor device element forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said semiconductor device element forming region.

83. The semiconductor substrate according to claim 74,

wherein said predetermined region extends over a single circuit block forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said circuit block forming region.

84. The semiconductor substrate according to claim 74,

wherein said semiconductor substrate is a silicon substrate.

76. (canceled)

79. (canceled)

85. A semiconductor substrate comprising an embedded insulating region comprising a combined, flat-shaped cavity present all over a predetermined region in a substrate,

wherein said cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface, and an inside part of said cavity includes no ion-implanted ions into said substrate in order to form said cavity, and

wherein a surface of said substrate is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate.

86. The semiconductor substrate according to claim 85, wherein said cavity self-aligns to at least one electrode present on said substrate.

87. The semiconductor substrate according to claim 85, wherein said cavity self-aligns to at least one isolation region present on said substrate.

88. The semiconductor substrate according to claim 85,

wherein said predetermined region extends over a single semiconductor device element forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said semiconductor device element forming region.

89. The semiconductor substrate according to claim 85,

wherein said predetermined region extends over a single circuit block forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said circuit block forming region.

90. The semiconductor substrate according to claim 85,

wherein said semiconductor substrate is a silicon substrate.

91. A semiconductor device comprising:

a semiconductor substrate comprising an embedded insulating region comprising a combined, flat-shaped cavity present all over a predetermined region,

wherein said cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface, wherein said inside surface is coated with at least an oxide film, said oxide film having a thicker film thickness in a portion, which is formed on side walls of said cavity than in a portion, which is formed on inside upper and lower surfaces of said cavity; and

at least one semiconductor device element which is present on a surface region of the semiconductor substrate on said embedded insulating region.

92. The semiconductor device according to claim 91, wherein a surface of said substrate is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate.

94. The semiconductor device according to claim 91, wherein said oxide film not only coats said inside surface of said cavity, but also includes at least one columnar portion extending in inner space of said cavity.

95. The semiconductor device according to claim 91, wherein said oxide film not only coats said inside surface of said cavity, but also includes at least one barrier-structure portion extending in inner space of said cavity.

96. The semiconductor device according to claim 91,

wherein inner space of said cavity is filled with said oxide film.

97. The semiconductor device according to claim 91,

wherein said cavity self-aligns to at least one electrode present on said substrate.

98. The semiconductor device according to claim 91,

wherein said cavity self-aligns to at least one isolation region present on said substrate.

99. The semiconductor device according to claim 91,

wherein said predetermined region extends over a single semiconductor device element forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said semiconductor device element forming region.

100. The semiconductor device according to claim 91,

wherein said predetermined region extends over a single circuit block forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said circuit block forming region.

101. The semiconductor device according to claim 91,

wherein said semiconductor substrate is a silicon substrate.

93. (canceled)

102. A semiconductor device comprising:

a semiconductor substrate comprising an embedded insulating region comprising a combined, flat-shaped cavity present all over a predetermined region,

wherein said cavity has a seamlessly uninterrupted inside surface, as well as has inner space completely closed from outside of said substrate by the inside surface, and an inside part of said cavity includes no ion-implanted ions into said substrate in order to form said cavity, and

wherein a surface of said substrate is flat, and an interface between an upper portion of said cavity and said substrate is parallel and flat to a flat surface of said substrate; and

at least one semiconductor device element which is present on a surface region of the semiconductor substrate on said embedded insulating region.

103. The semiconductor device according to claim 102, wherein said cavity self-aligns to at least one electrode present on said substrate.

104. The semiconductor device according to claim 102, wherein said cavity self-aligns to at least one isolation region present on said substrate.

105. The semiconductor device according to claim 102,

wherein said predetermined region extends over a single semiconductor device element forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said semiconductor device element forming region.

106. The semiconductor device according to claim 102,

wherein said predetermined region extends over a single circuit block forming region of said substrate, whereby an embedded insulating region comprising said cavity extends over said circuit block forming region.

107. The semiconductor device according to claim 102,

wherein said semiconductor substrate is a silicon substrate.