Corrosion-inhibiting cleaning compositions for metal layers and patterns on semiconductor substrates
First Claim
1. A corrosion-inhibiting cleaning composition for semiconductor wafer processing, comprising an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids.
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Abstract
A corrosion-inhibiting cleaning composition for semiconductor wafer processing includes an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is preferably in a range from about 0.0001 wt % to about 0.1 wt % and the quantity of the surfactant is preferably in a range from about 0.001 wt % to about 1.0 wt %. The aqueous admixture may also include sulfuric acid and a fluoride, which act as oxide etchants, and a peroxide, which acts as a metal etchant.
83 Citations
45 Claims
- 1. A corrosion-inhibiting cleaning composition for semiconductor wafer processing, comprising an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids.
- 12. A corrosion-inhibiting cleaning solution for semiconductor wafer processing, consisting essentially of a surfactant, a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids, first and second oxide etchants, a metal etchant and deionized water.
- 23. A corrosion-inhibiting cleaning composition for semiconductor wafer processing, comprising an aqueous admixture of at least an amino phosphonate, a surfactant, sulfuric acid, a fluoride, a peroxide and deionized water.
- 33. A cleaning composition for semiconductor processing, comprising an admixture of at least water, a surfactant and a corrosion-inhibiting compound having the following formula:
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37. A method of forming an integrated circuit device, comprising the steps of:
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forming a gate oxide layer on an integrated circuit substrate;
forming a tungsten metal layer on the gate oxide layer;
patterning the tungsten metal layer and gate oxide layer to define a tungsten-based insulated gate electrode; and
exposing the patterned tungsten metal layer to a cleaning solution comprising a surfactant, a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids, first and second oxide etchants, a metal etchant and deionized water. - View Dependent Claims (38, 39, 40)
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41. A method of forming a memory device, comprising the steps of:
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forming an interlayer dielectric layer on an integrated circuit substrate;
forming an interconnect opening in the interlayer dielectric layer;
filling the interconnect opening with a conductive plug;
forming a bit line node electrically coupled to the conductive plug;
exposing the bit line node to a cleaning solution comprising a surfactant, a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids, first and second oxide etchants, a metal etchant and deionized water. - View Dependent Claims (42, 43, 44)
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45. A method of forming an integrated circuit device, comprising the steps of:
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forming a gate oxide layer on an integrated circuit substrate;
forming a tungsten metal layer on the gate oxide layer;
patterning the tungsten metal layer and gate oxide layer to define a tungsten-based insulated gate electrode; and
exposing the patterned tungsten metal layer to a cleaning solution consisting essentially of a surfactant, a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids, hydrogen fluoride, hydrogen peroxide, sulfuric acid and deionized water.
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Specification