Arbitration system having a packet memory and method for memory responses in a hub-based memory system
First Claim
1. A memory hub, comprising:
- a decoder being operable to receive memory requests and to determine a memory request identifier associated with each memory request;
a packet memory coupled to the decoder, the packet memory being operable to receive memory request identifiers from the decoder and to store the received memory request identifiers;
a packet tracker coupled to the packet memory, the packet memory being operable to receive remote memory responses and to associate each received remote memory response with a memory request identifier stored in the packet memory, the packet tracker being operable to cause the memory request identifier to be effectively removed from the packet memory;
a multiplexor being operable to couple either the received remote memory responses or the local memory responses to an output responsive to a control signal; and
arbitration control logic coupled to the multiplexor and the packet memory and being operable to generate the control signal.
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0 Petitions
Accused Products
Abstract
A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers and stores the memory request identifiers. A packet tracker receives remote memory responses and associates each remote memory response with a memory request identifier and removes the memory request identifier from the packet memory. A multiplexor receives remote memory responses and local memory responses. The multiplexor selects an output responsive to a control signal. Arbitration control logic is coupled to the multiplexor and the packet memory and develops the control signal to select a memory response for output.
164 Citations
33 Claims
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1. A memory hub, comprising:
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a decoder being operable to receive memory requests and to determine a memory request identifier associated with each memory request;
a packet memory coupled to the decoder, the packet memory being operable to receive memory request identifiers from the decoder and to store the received memory request identifiers;
a packet tracker coupled to the packet memory, the packet memory being operable to receive remote memory responses and to associate each received remote memory response with a memory request identifier stored in the packet memory, the packet tracker being operable to cause the memory request identifier to be effectively removed from the packet memory;
a multiplexor being operable to couple either the received remote memory responses or the local memory responses to an output responsive to a control signal; and
arbitration control logic coupled to the multiplexor and the packet memory and being operable to generate the control signal. - View Dependent Claims (2, 3, 4, 5)
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- 6. A memory hub being operable to receive local memory responses and remote memory responses, the memory hub being operable to store the received memory responses and to apply an arbitration algorithm to select the order in which the stored local and remote memory responses are provided on an uplink output based on the ages of memory requests corresponding to the stored local and remote memory responses.
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11. A memory module, comprising:
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a plurality of memory devices; and
a memory hub coupled to the memory devices, the memory hub comprising;
a decoder adapted to receive memory requests and being operable to determine a memory request identifier associated with each memory request;
a packet memory adapted to receive memory request identifiers and store the memory request identifiers;
a packet tracker adapted to receive remote memory responses and being operable to associate each remote memory response with a memory request identifier and remove the memory request identifier from the packet memory;
a multiplexor adapted to receive remote memory responses and local memory responses and being operable to select an output responsive to a control signal; and
arbitration control logic coupled to the multiplexor and the packet memory and being operable to generate the control signal to control selection of which memory response to output. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A memory system, comprising:
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a memory hub controller;
a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed links, at least one of the memory modules being coupled to the memory hub controller through a respective high-speed link, and each memory module comprising;
a plurality of memory devices; and
a memory hub coupled to the memory devices, the memory hub comprising, a decoder adapted to receive memory requests and being operable to determine a memory request identifier associated with each memory request;
a packet memory adapted to receive memory request identifiers and store the memory request identifiers;
a packet tracker adapted to receive remote memory responses and being operable to associate each remote memory response with a memory request identifier and remove the memory request identifier from the packet memory;
a multiplexor adapted to receive remote memory responses and local memory responses and being operable to select an output responsive to a control signal; and
arbitration control logic coupled to the multiplexor and the packet memory and being operable to generate the control signal to control selection of which memory response to output. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24. A computer system, comprising:
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a processor;
a system controller coupled to the processor, the system controller including a memory hub controller;
an input device coupled to the processor through the system controller;
an output device coupled to the processor through the system controller;
a storage device coupled to the processor through the system controller;
a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed links, at least one of the memory modules being coupled to the memory hub controller through a respective high-speed link, and each memory module comprising;
a plurality of memory devices; and
a memory hub coupled to the memory devices and coupled to the corresponding high-speed links, the memory hub including, a decoder adapted to receive memory requests and being operable to determine a memory request identifier associated with each memory request;
a packet memory adapted to receive memory request identifiers and store the memory request identifiers;
a packet tracker adapted to receive remote memory responses and being operable to associate each remote memory response with a memory request identifier and remove the memory request identifier from the packet memory;
a multiplexor adapted to receive remote memory responses and local memory responses and being operable to select an output responsive to a control signal; and
arbitration control logic coupled to the multiplexor and the packet memory and being operable to generate the control signal to control selection of which memory response to output. - View Dependent Claims (25, 26, 27, 28)
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29. A method of processing and forwarding memory responses in a memory system including a plurality of memory modules, each memory module including a memory hub coupled to memory devices, the method comprising:
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receiving memory requests, each having a memory request identifier;
storing the memory request identifiers;
storing local memory responses from the memory devices;
storing remote memory responses from remote memory modules;
applying in at least one hub an arbitration algorithm based on the ages of the stored memory request identifiers to determine an order in which the stored local and remote memory responses are forwarded to an upstream memory module; and
forwarding the local and remote memory responses upstream according to the determined order. - View Dependent Claims (30, 31, 32, 33)
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Specification