Semiconductor integrated circuits with stacked node contact structures and methods of fabricating such devices

• US 20050179061A1
• Filed: 01/11/2005
• Published: 08/18/2005
• Est. Priority Date: 01/12/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Soon-Moon, Jang, Jae-Hoon, Hwang, Byung-Jun, Kwak, Kun-Ho
• Granted Patent: US 7,479,673 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

Claims

1. An integrated circuit comprising:

a first transistor having first and second impurity regions formed at a semiconductor substrate;

a first interlayer insulating layer on the first transistor;

a second transistor having first and second impurity regions on the first interlayer insulating layer opposite the first transistor;

a second interlayer insulating layer on the second transistor opposite the first interlayer insulating layer;

a third transistor having first and second impurity regions on the second interlayer insulating layer opposite the second transistor;

a third interlayer insulating layer on the third transistor opposite the second interlayer insulating layer; and

a node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first transistor, the first impurity region of the second transistor and the first impurity region of third transistor to one another.

2. The integrated circuit as recited in claim 1, wherein the second transistor overlaps the first transistor, and wherein the third transistor overlaps the second transistor.

3. The integrated circuit as recited in claim 1, wherein the first transistor comprises a bulk transistor and wherein the second and third transistors comprise thin film transistors.

4. The integrated circuit as recited in claim 3, wherein the second and third transistors each comprise single crystalline thin film transistors.

5. The integrated circuit as recited in claim 1, further comprising:

a lower node semiconductor plug between the first impurity region of the second transistor and the first impurity region of the first transistor; and

an upper node semiconductor plug between the first impurity region of the third transistor and the first impurity region of the second transistor,

wherein the node plug also is electrically connected to the lower and upper node semiconductor plugs.

6. The integrated circuit as recited in claim 5, wherein the lower and upper node semiconductor plugs each comprise single crystalline semiconductor plugs, and the node plug comprises a metal plug.

7. The integrated circuit as recited in claim 6, wherein the node plug forms an ohmic contact with respect to both P-type semiconductor and N-type semiconductor materials.

8. The integrated circuit as recited in claim 7, wherein the metal plug comprises a tungsten plug.

9. The integrated circuit as recited in claim 8, wherein the metal plug further comprises a barrier metal layer surrounding the tungsten plug.

10. The integrated circuit as recited in claim 5, wherein the lower node semiconductor plug and the first impurity region of the first transistor are of same conductivity type.

11. The integrated circuit as recited in claim 5, wherein the lower node semiconductor plug and the first impurity region of the first transistor have different conductivity types, and wherein the node plug is in direct contact with the first impurity region of the first transistor.

12. A static random access memory (SRAM) cell comprising:

a first bulk transistor having a first impurity region formed at least partially in a semiconductor substrate;

a second bulk transistor having a first impurity region formed at least partially in the semiconductor substrate;

a first interlayer insulating layer on the first and second bulk transistors;

a first lower thin film transistor having a first impurity region on the first interlayer insulating layer;

a second lower thin film transistor having a first impurity region on the first interlayer insulating layer;

a second interlayer insulating layer on the first and second lower thin film transistors;

a first upper thin film transistor having a first impurity region on the second interlayer insulating layer;

a second upper thin film transistor having a first impurity region on the second interlayer insulating layer;

a third interlayer insulating layer on the first and second upper thin film transistors;

a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first bulk transistor, the first impurity region of the first lower thin film transistor and the first impurity region of the first upper thin film transistor to one another; and

a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect the first impurity region of the second bulk transistor, the first impurity region of the second lower thin film transistor and the first impurity region of the second upper thin film transistor to one another.

13. The SRAM cell as recited in claim 12, wherein the first lower thin film transistor overlaps the first bulk transistor and wherein the second lower thin film transistor overlaps the second bulk transistor, and wherein the first upper thin film transistor overlaps the first lower thin film transistor, and wherein the second upper thin film transistor overlaps the second lower thin film transistor.

14. The SRAM cell as recited in claim 12, wherein the first and second lower thin film transistors and the first and second upper thin film transistors each comprise single crystalline thin film transistors.

15. The SRAM cell as recited in claim 12, further comprising:

a first lower node semiconductor plug between the first impurity region of the first lower thin film transistor and the first impurity region of the first bulk transistor;

a first upper node semiconductor plug between the first impurity region of the first upper thin film transistor and the first impurity region of the first lower thin film transistor;

a second lower node semiconductor plug between the first impurity region of the second lower thin film transistor and the first impurity region of the second bulk transistor; and

a second upper node semiconductor plug between the first impurity region of the second upper thin film transistor and the first impurity region of the second lower thin film transistor,

wherein the first node plug is electrically connected to the first lower node semiconductor plug and the first upper node semiconductor plug, and wherein the second node plug is electrically connected to the second lower node semiconductor plug and the second upper node semiconductor plug.

16. The SRAM cell as recited in claim 15, wherein the first and second upper node semiconductor plugs and the first and second lower node semiconductor plugs each comprise single crystalline semiconductor plugs, and wherein the first and second node plugs each comprise metal plugs.

17. The SRAM cell as recited in claim 16, wherein the first and second node plugs each form an ohmic contact with respect to both P-type semiconductor and N-type semiconductor materials.

18. The SRAM cell as recited in claim 16, wherein the first and second node plugs each comprise a tungsten plug.

19. The SRAM cell as recited in claim 18, wherein each of the first and second node plugs further comprises a barrier metal layer surrounding the tungsten plug.

20. The SRAM cell as recited in claim 15, wherein the first lower node semiconductor plug has the same conductivity type as the first impurity region of the first bulk transistor and the second lower node semiconductor plug has the same conductivity type as the first impurity region of the second bulk transistor.

21. The SRAM cell as recited in claim 15, wherein the first lower node semiconductor plug has a different conductivity type than does the first impurity region of the first bulk transistor, and wherein the second lower node semiconductor plug has a different conductivity type than does the first impurity region of the second bulk transistor, and wherein the first node plug is in direct contact with the first impurity region of the first bulk transistor, and wherein the second node plug is in direct contact with the first impurity region of the second bulk transistor.

22. The SRAM cell as recited in claim 12, wherein the first and second bulk transistors comprise first and second N-channel driver transistors, respectively, and wherein the first impurity region of the first bulk transistor comprises the drain region of the first bulk transistor, and wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor.

23. The SRAM cell as recited in claim 22, wherein the first N-channel driver transistor has a gate electrode that is electrically connected to the second node plug, and wherein the second N-channel driver transistor has a gate electrode that is electrically connected to the first node plug.

24. The SRAM cell as recited in claim 23, wherein the first and second lower thin film transistors comprise first and second P-channel load transistors, respectively, and wherein the first and second upper thin film transistors comprise first and second N-channel transfer transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a drain region of the first lower thin film transistor, and wherein the first impurity region of the second lower thin film transistor comprises a drain region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a source region of the first upper thin film transistor and wherein the first impurity region of the second upper thin film transistor comprises a source region of the second upper thin film transistor.

25. The SRAM cell as recited in claim 24, wherein the first P-channel load transistor has a gate electrode that is electrically connected to the second node plug, and the second P-channel load transistor has a gate electrode that is electrically connected to the first node plug.

26. The SRAM cell as recited in claim 24, wherein the first and second N-channel transfer transistors have gate electrodes that are electrically connected to each other to act as a word line.

27. The SRAM cell as recited in claim 24, further comprising:

a ground line that is electrically connected to the source regions of the first and second N-channel driver transistors; and

a power line that is electrically connected to the source regions of the first and second P-channel load transistors;

wherein the ground line and the power line are substantially in parallel with a gate electrode of the first N-channel driver transistor and with a gate electrode of the second N-channel driver transistor.

28. The SRAM cell as recited in claim 25, further comprising:

a first bit line that is electrically connected to the drain region of the first N-channel transfer transistor; and

a second bit line that is electrically connected to the drain region of the second N-channel transfer transistor;

wherein the first and second bit lines cross over the power line and the ground line.

29. The SRAM cell as recited in claim 28, wherein the first bit line is substantially perpendicular to a gate electrode of the first N-channel driver transistor, a gate electrode of the first P-channel load transistor and a gate electrode of the first N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate, and the second bit line is substantially perpendicular to a gate electrode of the second N-channel driver transistor, a gate electrode of the second P-channel load transistor and a gate electrode of the second N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate.

30. The SRAM cell as recited in claim 23, wherein the first and second lower thin film transistors comprise first and second N-channel transfer transistors, respectively, and wherein the first and second upper thin film transistors comprise first and second P-channel load transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a source region of the first lower thin film transistor, and wherein the first impurity region of the second lower thin film transistor comprises a source region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a drain region of the first upper thin film transistor and wherein the first impurity region of the second upper thin film transistor comprises a drain region of the second upper thin film transistor.

31. The SRAM cell as recited in claim 30, wherein the first P-channel load transistor has a gate electrode that is electrically connected to the second node plug, and wherein the second P-channel load transistor has a gate electrode that is electrically connected to the first node plug.

32. A static random access memory (SRAM) cell comprising:

an isolation layer in a semiconductor substrate that defines first and second active regions;

a first bulk transistor and a second bulk transistor at least partially in the first and second active regions, respectively;

a first interlayer insulating layer on the first and second bulk transistors;

a first single crystalline lower body pattern and a second single crystalline lower body pattern on the first interlayer insulating layer;

a first lower thin film transistor and a second lower thin film transistor at the first and second lower body patterns, respectively;

a second interlayer insulating layer on the first and second lower thin film transistors;

a first single crystalline upper body pattern and a second single crystalline upper body pattern on the second interlayer insulating layer;

a first upper thin film transistor and a second upper thin film transistor at the first and second upper body patterns, respectively;

a third interlayer insulating layer on the first and second upper thin film transistors;

a first node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the first bulk transistor, a first impurity region of the first lower thin film transistor and a first impurity region of the first upper thin film transistor to one another; and

a second node plug penetrating the first, second and third interlayer insulating layers to electrically connect a first impurity region of the second bulk transistor, a first impurity region of the second lower thin film transistor and a first impurity region of the second upper thin film transistor to one another.

33. The SRAM cell as recited in claim 32, wherein the first and second bulk transistors comprise first and second N-channel driver transistors, respectively, and wherein the first impurity region of the first bulk transistor comprises the drain region of the first bulk transistor, and wherein the first impurity region of the second bulk transistor comprises the drain region of the second bulk transistor.

34. The SRAM cell as recited in claim 33, wherein the first N-channel driver transistor has a gate electrode that is electrically connected to the second node plug, and wherein the second N-channel driver transistor has a gate electrode that is electrically connected to the first node plug.

35. The SRAM cell as recited in claim 33, further comprising:

a first ground active region extending from a first end of the first active region in a direction perpendicular to the first active region; and

a second ground active region extending from a first end of the second active region in a direction perpendicular to the second active region.

36. The SRAM cell as recited in claim 35, wherein the first and second lower thin film transistors are first and second P-channel load transistors, respectively, and wherein the first and second upper thin film transistors are first and second N-channel transfer transistors, respectively, and wherein the first impurity region of the first lower thin film transistor comprises a drain region of the first lower thin film transistor, and wherein the second lower thin film transistor comprises a drain region of the second lower thin film transistor, and wherein the first impurity region of the first upper thin film transistor comprises a source region of the first upper thin film transistor, and wherein the first impurity region of the second upper thin film transistor comprises a source region of the second upper thin film transistor.

37. The SRAM cell as recited in claim 36, wherein the first lower body pattern overlaps the first active region, and wherein the second lower body pattern overlaps the second active region, and wherein the first upper body pattern overlaps the first lower body pattern, and wherein the second upper body pattern overlaps the second lower body pattern.

38. The SRAM cell as recited in claim 37, wherein a gate electrode of the first load transistor overlaps a gate electrode of the first driver transistor, and wherein a gate electrode of the second load transistor overlaps the gate electrode of the second driver transistor, and wherein the gate electrode of the first load transistor is electrically connected to the second node plug, and wherein the gate electrode of the second load transistor is electrically connected to the first node plug.

39. The SRAM cell as recited in claim 37, wherein the first lower body pattern further includes an extension that overlaps a portion of the first ground active region, and wherein the second lower body pattern further includes an extension that overlaps a portion of the second ground active region.

40. The SRAM cell as recited in claim 36, wherein a gate electrode of the first transfer transistor is electrically connected to a gate electrode of the second transfer transistor to act as a word line.

41. The SRAM cell as recited in claim 35, further comprising:

a ground line that is electrically connected to the first and second ground active regions;

wherein the ground line crosses over the first and second active regions.

42. The SRAM cell as recited in claim 39, further comprising:

a power line that is electrically connected to the extensions of the first and second lower body patterns, wherein the power line crosses over the first and second active regions.

43. The SRAM cell as recited in claim 36, further comprising:

a first bit line and a second bit line that is parallel to the first bit line,

wherein the first bit line is electrically connected to a drain region of the first transfer transistor;

wherein the second bit line is electrically connected to a drain region of the second transfer transistor; and

wherein the first and second bit lines cross over the first and second ground active regions.

44. The SRAM cell as recited in claim 43, wherein the first bit line is substantially perpendicular to a gate electrode of the first N-channel driver transistor, a gate electrode of the first P-channel load transistor and a gate electrode of the first N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate, and wherein the second bit line is substantially perpendicular to a gate electrode of the second N-channel driver transistor, a gate electrode of the second P-channel load transistor and a gate electrode of the second N-channel transfer transistor when viewed from an axis that is perpendicular to the primary plane of the semiconductor substrate.

45-70. -70. (canceled)

71. A method of fabricating an integrated circuit, the method comprising:

forming a first transistor having first and second impurity regions at a semiconductor substrate;

forming a first interlayer insulating layer on the first transistor;

forming a second transistor having first and second impurity regions on the first interlayer insulating layer opposite the first transistor;

forming a second interlayer insulating layer on the second transistor opposite the first interlayer insulating layer;

forming a third transistor having first and second impurity regions on the second interlayer insulating layer opposite the second transistor;

forming a third interlayer insulating layer on the third transistor opposite the second interlayer insulating layer; and

forming a node plug that penetrates the first, second and third interlayer insulating layers to electrically connect the first impurity region of the first transistor, the first impurity region of the second transistor and the first impurity region of third transistor to one another.

72-81. -81. (canceled)