Semiconductor device and method for fabricating the same

• US 20050179082A1
• Filed: 01/10/2005
• Published: 08/18/2005
• Est. Priority Date: 02/16/2004
• Status: Active Grant

• Current Assignee: Collabo Innovations, Inc. (Wi-LAN Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mizokuchi, Shuji, Miyata, Satoe
• Granted Patent: US 7,626,229 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes: a semiconductor substrate; a first semiconductor region formed in the reverse surface region of the semiconductor substrate and including a first conductivity type impurity; a second semiconductor region formed on the first semiconductor region in the semiconductor substrate and including a second conductivity type impurity; a third semiconductor region formed on the second semiconductor region in the semiconductor substrate and including a first conductivity type impurity; a trench passing through the second and third semiconductor regions and reaching the first semiconductor region; and a gate insulating film formed along the wall face of the trench; a gate electrode formed on the gate insulating film in the trench. Further, a pocket region including a second conductivity type impurity of which peak concentration is higher than that of the second semiconductor region is formed by a side of the trench between the second semiconductor region and the third semiconductor region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first semiconductor region formed in a reverse surface region of said semiconductor substrate and including a first conductivity type impurity;

a second semiconductor region formed on said first semiconductor region in said semiconductor substrate and including a second conductivity type impurity;

a third semiconductor region formed on said second semiconductor region in the semiconductor substrate and including a first conductivity type impurity;

a trench passing through said second semiconductor region and third semiconductor region and reaching said first semiconductor region;

a gate insulating film formed along a side wall of said trench;

a gate electrode formed on said gate insulating film in said trench; and

a pocket region formed by a side of said trench between said second semiconductor region and said third semiconductor region and including a second conductivity type impurity of which peak concentration is higher than that of said second semiconductor region.

2. The semiconductor device of claim 1, wherein

said gate electrode is formed at a part other than a upper part of said trench, and

an insulating film is provided for burying the upper part of said trench.

3. The semiconductor device of claim 1, wherein

said pocket region is formed only in a region near a wall face of said trench.

4. The semiconductor device of claim 1, wherein

said pocket region is formed over an entire region between said second semiconductor region and said third semiconductor region.

5. A semiconductor device fabrication method, comprising the steps of:

a step (a) of forming a first semiconductor region including a first conductivity type impurity in a reverse surface region of a semiconductor substrate;

a step (b) of forming a second semiconductor region including a second conductivity type impurity on said first semiconductor region in said semiconductor substrate;

a step (c) of forming a trench that passes through said second semiconductor region and reaches said first semiconductor region by selectively digging said semiconductor substrate;

a step (d) of forming a gate insulating film along a wall face of said trench;

a step (e) of forming a gate electrode on said gate insulating film by burying a conductive film in said trench;

a step (f) of forming a third semiconductor region by introducing a first conductivity type impurity into an upper part of said second semiconductor region; and

a step (g) of forming, after said step (e) and before or after said step (f), a pocket region, of which peak concentration is higher than that of said second semiconductor region, between said second semiconductor region and said third semiconductor region by ion implantation of a second conductivity type impurity.

6. The semiconductor device fabrication method of claim 5, wherein,

in said step (e), said gate electrode is formed at a part other than the upper part of said trench, and

in said step (g), said pocket region is formed only in a region near a wall face of said trench by performing ion implantation of a second conductivity type impurity in a direction tilted against a direction perpendicular to a plane of said substrate after an introducing mask for covering a region of said semiconductor substrate other than said trench is formed.

7. The semiconductor device fabrication method of claim 6, further comprising the step of:

burying an insulating film at a part above said gate electrode in said trench after said step (g) and before or after said step (f).

8. The semiconductor device fabrication method of claim 6, wherein

in said step (g), the tilt angle of the ion implantation with respect to the direction perpendicular to the plane of said substrate is set within a range between 7 degrees and 45 degrees.

9. The semiconductor device fabrication method of claim 8, wherein

in said step (g), two-step, four-step or eight step ion implantation is performed.

10. The semiconductor device fabrication method of claim 5, wherein

in said step (e), said gate electrode is formed at a part other than an upper part of said trench,

a step of burying an insulating film on said gate electrode in said trench is performed additionally before or after said step (f) and said step (g) or is performed between said step (f) and said step (g), and

in said step (g), said pocket region is formed in an entire region between said second semiconductor region and said third semiconductor region by performing ion implantation of a second conductivity type impurity to an entirety of said semiconductor substrate.

11. The semiconductor device fabrication method of claim 10, wherein

a step of burying said insulating film on said gate electrode in said trench is performed additionally after said step (e) and before or after said step (f).