Display apparatus and driver circuit of display apparatus
First Claim
1. A driver circuit of a display apparatus, comprising:
- a writing circuit having a plurality of first switches respectively provided for signal supply lines of the display apparatus, said writing circuit being provided for inputting a write signal into each of said signal supply lines by conducting each of said plurality of first switches;
a shift register having flip-flops of plural stages, said shift register being provided for sequentially outputting a timing pulse from each of said flip-flops of plural stages to conduct each of said first switches; and
a pre-charge circuit having a plurality of second switches respectively provided for the signal supply lines, said pre-charge circuit being provided for pre-charging each of said signal supply lines by conducting each of said plurality of second switches, wherein said shift register includes a plurality of pulse signal supply circuits provided corresponding to said signal supply lines to be pre-charged while an input operation of the write signal is being carried out, and each of said pulse signal supply circuits receives a clock signal different from the timing pulse, in response to an input of the timing pulse as outputted from each of said flip-flops, and outputs as a pre-charge pulse, a pulse signal in sync with the clock signal to a second switch corresponding to a prescribed signal supply line to which the input operation of the write signal is not being carried out to conduct said second signal; and
in each output line of the timing pulse, provided is a superimposition preventing section made up of a superimposition removing circuit for removing from the timing pulse to be supplied to the output line, an overlapped part which is overlapped with the pre-charge pulse for pre-charging the signal supply line to which the input operation of the write signal is to be carried out by the timing pulse.
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Accused Products
Abstract
A driver circuit of a display apparatus is provided with a nor circuit in each output line of a timing pulse. To the nor circuit, inputted are a timing pulse to be supplied to the output line and a pre-charge pulse for pre-charging a data signal line SL to which a write signal is being inputted based on the timing pulse. With this structure, it is possible to realize a driver circuit storing a pre-charge circuit of a display apparatus, which can surely prevent a collision between a pre-charge potential and a potential of a video signal in a signal supply line when pre-charging the signal supply line from a pre-charge power supply of a small driving performance, while maintaining the number of stages in the shift register to be the required minimum number
25 Citations
27 Claims
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1. A driver circuit of a display apparatus, comprising:
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a writing circuit having a plurality of first switches respectively provided for signal supply lines of the display apparatus, said writing circuit being provided for inputting a write signal into each of said signal supply lines by conducting each of said plurality of first switches;
a shift register having flip-flops of plural stages, said shift register being provided for sequentially outputting a timing pulse from each of said flip-flops of plural stages to conduct each of said first switches; and
a pre-charge circuit having a plurality of second switches respectively provided for the signal supply lines, said pre-charge circuit being provided for pre-charging each of said signal supply lines by conducting each of said plurality of second switches, wherein said shift register includes a plurality of pulse signal supply circuits provided corresponding to said signal supply lines to be pre-charged while an input operation of the write signal is being carried out, and each of said pulse signal supply circuits receives a clock signal different from the timing pulse, in response to an input of the timing pulse as outputted from each of said flip-flops, and outputs as a pre-charge pulse, a pulse signal in sync with the clock signal to a second switch corresponding to a prescribed signal supply line to which the input operation of the write signal is not being carried out to conduct said second signal; and
in each output line of the timing pulse, provided is a superimposition preventing section made up of a superimposition removing circuit for removing from the timing pulse to be supplied to the output line, an overlapped part which is overlapped with the pre-charge pulse for pre-charging the signal supply line to which the input operation of the write signal is to be carried out by the timing pulse. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A display apparatus comprising:
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a plurality of pixels;
a plurality of data signal lines which serve as a plurality of signal supply lines, said plurality of data signal lines being provided so as to correspond to said plurality of pixels;
a plurality of scanning signal lines which serve as a plurality of signal supply lines, said plurality of scanning signal lines being provided so as to correspond to said plurality of pixels, a data signal line driver for writing a video signal as a write signal in said plurality of data signal lines and said plurality of pixels; and
a scanning signal line driver for writing a scanning signal as a write signal in said plurality of scanning signal lines for selecting a pixel to which the video signal is written, wherein said data signal line driver comprises;
a writing circuit having a plurality of first switches respectively provided for signal supply lines of the display apparatus, said writing circuit being provided for inputting a write signal into each of said signal supply lines by conducting each of said plurality of first switches;
a shift register having flip-flops of plural stages, said shift register being provided for sequentially outputting a timing pulse from each of said flip-flops of plural stages to conduct each of said first switches; and
a pre-charge circuit having a plurality of second switches respectively provided for the signal supply lines, said pre-charge circuit being provided for pre-charging each of said signal supply lines by conducting each of said plurality of second switches, wherein said shift register includes a plurality of pulse signal supply circuits provided corresponding to said signal supply lines to be pre-charged while an input operation of the write signal is being carried out, and each of said pulse signal supply circuits receives a clock signal different from the timing pulse, in response to an input of the timing pulse as outputted from each of said flip-flops, and outputs as a pre-charge pulse, a pulse signal in sync with the clock signal to a second switch corresponding to a prescribed signal supply line to which the input operation of the write signal is not being carried out to conduct said second signal; and
in each output line of the timing pulse, provided is a superimposition preventing section made up of a superimposition removing circuit for removing from the timing pulse to be supplied to the output line, an overlapped part which is overlapped with the pre-charge pulse for pre-charging the signal supply line to which the input operation of the write signal is to be carried out by the timing pulse. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification