Graphics Controller Integrated Circuit without Memory Interface
3 Assignments
0 Petitions
Accused Products
Abstract
A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.
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Citations
51 Claims
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1-11. -11. (canceled)
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12. An integrated circuit comprising:
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a first dopant-type semiconductor substrate having a logic portion and a memory portion thereon, the logic portion having at least 30K logic gates and having a layout on the substrate that need not be constrained by the physical dimensions of the layout of the memory portion on the substrate, the memory portion coupled to the logic portion through a data interface, the memory portion having a capacity of at least 2 megabits and the data interface being at least 128 bits wide, and a capacitor having a first dopant-type transistor in a second dopant-type well in the first dopant-type semiconductor substrate, the first dopant-type transistor having a gate, first and second source/drains, the first source/drain connected in common to the second source/drain to form a first terminal of the capacitor, the gate forming a second terminal of the capacitor, the second dopant-type well connected to a first voltage supply line, and the substrate connected to a second voltage supply line, different voltages applied to the first voltage supply line and to the second voltage supply line, such that the semiconductor junction between the second dopant-type well and the substrate is reverse-biased;
whereby the capacitor is isolated from electrical noise in the substrate. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. An integrated circuit comprising:
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a first dopant-type semiconductor substrate having a logic portion and a memory portion thereon, the logic portion having at least 30K logic gates and a layout on the substrate that need not be constrained by the physical dimensions of the layout of the memory portion on the substrate, the memory portion coupled to the logic portion through a data interface, the memory portion having a capacity of at least 2 megabits and the data interface being at least 128 bits wide, and an analog circuit having a capacitor, the capacitor comprising a first dopant-type transistor in a second dopant-type well in the first dopant-type semiconductor substrate, the first dopant-type transistor having a gate, first and second source/drains, the first source/drain connected in common to the second source/drain to form a first terminal of the capacitor, the gate forming a second terminal of the capacitor, the second dopant-type well connected to a first voltage supply line, and the substrate connected to a second voltage supply line, different voltages applied to the first voltage supply line and to the second voltage supply line, such that the semiconductor junction between the second dopant-type well and the substrate is reverse-biased;
whereby the capacitor is isolated from electrical noise in the substrate. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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28. A complementary MOS integrated circuit, containing NMOS transistors and PMOS transistors on a semiconductor substrate, comprising:
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circuitry for processing data associated with graphics information for display by an electronic system in which the complementary MOS integrated circuit resides, the circuitry including at least 30K logic gates in a layout on the substrate;
a memory for storing and retrieving at least a portion of data associated with the graphics information for display by the electronic system in which the complementary MOS integrated circuit resides, the memory having a capacity of at least 2 megabits in a layout on the substrate, the circuitry for processing data having a layout on the substrate that need not be constrained by the physical dimensions of the layout of the memory portion on the substrate; and
a data interface between the circuitry and the memory, the data interface being at least 128 bits wide;
whereby integration of the circuitry, the memory and the data interface in the complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in the electronic system in which the complementary MOS integrated circuit resides. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A complementary MOS integrated circuit, containing NMOS transistors and PMOS transistors on a semiconductor substrate, comprising:
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circuitry for processing, controlling or manipulating video data for display by an electronic system in which the complementary MOS integrated circuit resides, the circuitry including at least 30K logic gates in a layout on the substrate;
a memory for storing and retrieving at least a portion of the video data for display by the electronic system in which the complementary MOS integrated circuit resides, the memory having a capacity of at least 2 megabits in a layout on the substrate; and
a data interface between the circuitry and the memory, the data interface being at least 128 bits wide in a layout on the substrate, and wherein the layout on the substrate for the circuitry for processing, controlling or manipulating video data need not be constrained by the physical dimensions of the layout of the memory on the substrate;
whereby integration of the circuitry, the memory and the data interface in the complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in the electronic system in which the complementary MOS integrated circuit resides. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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Specification