Method and system for fast memory access

• US 20050180240A1
• Filed: 04/11/2005
• Published: 08/18/2005
• Est. Priority Date: 06/29/2001
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Beat, Robert
• Application Number:
  US11/102,641
• Publication Number:
  US 20050180240A1
• Time in Patent Office: Days
• US Class Current: 365/221
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

Claims

1-37. -37. (canceled)

38. A method of accessing a misaligned data word, comprising:

simultaneously providing a first address to a first memory section using a first address bus and a second address that is not equal to the first address to a second memory section using a second address bus; and

accessing the misaligned data word by performing at least one of a simultaneous read operation from the first and second memory sections and a simultaneous write operation to the first and second memory sections;

wherein accessing the misaligned data word includes

reading a first portion of the misaligned data word from the first memory section, and

reading a second portion of the misaligned data word from the second memory section.

39. The method of claim 38, further comprising:

assembling a word using the first and second word portions.

40. A method of accessing a misaligned data word, comprising:

simultaneously providing a first address to a first memory section using a first address bus and a second address that is not equal to the first address to a second memory section using a second address bus; and

accessing the misaligned data word by performing at least one of a simultaneous read operation from the first and second memory sections and a simultaneous write operation to the first and second memory sections;

wherein accessing the misaligned data word includes

writing a first portion of the misaligned data word to the first memory section, and

writing a second portion of the misaligned data word to the second memory section.

41. The method of claim 40, wherein writing the first portion and writing the second portion are performed in response to performing a shift operation on the misaligned data word.

42. The method of claim 40, further comprising:

providing write control information signals to a plurality of first modules of the first memory section, whereby write operations are activated on only those first modules designated for data word information.

43. A method of accessing a misaligned data word, comprising:

simultaneously providing a first address to a first memory section including a first number of bits using a first address bus and a second address that is not equal to the first address to a second memory section including a second number of bits that is same as the first number of bits using a second address bus; and

accessing the misaligned data word by performing at least one of a simultaneous read operation from the first and second memory sections and a simultaneous write operation to the first and second memory sections;

wherein accessing the misaligned data word is performed in a single cycle.

44. A method of accessing a misaligned data word, comprising:

simultaneously providing a first address to a first memory section using a first address bus and a second address that is one address location greater than the first address to a second memory section using a second address bus; and

accessing the misaligned data word by performing at least one of a simultaneous read operation from the first and second memory sections and a simultaneous write operation to the first and second memory sections;

wherein accessing the misaligned data word is performed in a single cycle.

45. The method of claim 44, wherein simultaneously providing the first address and the second address is performed using the first and second address busses having at least one disjoint address line.

46. The method of claim 44, wherein simultaneously providing the first address and the second address is performed using the first and second address busses having at least a plurality of disjoint address lines.

47. The method of claim 46, wherein simultaneously providing the first address and the second address is performed using the first and second address busses having completely disjoint address lines.

48. A method of accessing a misaligned data word, comprising:

simultaneously providing a first address to a first memory section using a first address bus and a second address that is not equal to the first address to a second memory section using a second address bus;

accessing the misaligned data word by performing at least one of a simultaneous read operation from the first and second memory sections and a simultaneous write operation to the first and second memory sections; and

providing a plurality of read control information signals to a plurality of first modules of the first memory section, whereby read operations are activated on only those first modules containing word data;

wherein accessing the misaligned data word is performed in a single cycle.

49. The method of claim 48, further comprising:

providing a plurality of write control information signals to the plurality of first modules of the first memory section, whereby write operations are activated on only those first modules designated for data word information.

50. A method of accessing a misaligned data word stored in first and second separately addressable memory arrays, comprising:

storing a first portion of the misaligned data word at a first location of a first memory array that includes even address locations;

storing a second portion of the misaligned data word at a second location of a second memory array that includes odd address locations;

simultaneously providing a first address indicating the first location to the first memory array and a second address indicating the second location to the second memory array; and

accessing the misaligned data word by performing at least one of a simultaneous read operation from the first and second memory arrays and a simultaneous write operation to the first and second memory arrays;

wherein accessing the misaligned data word is performed in a single cycle.