Word line arrangement having segmented word lines

• US 20050180244A1
• Filed: 04/11/2005
• Published: 08/18/2005
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Granted Patent: US 7,002,825 B2
• Time in Patent Office: Days
• US Class Current: 365/225.700
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Claims

1. An integrated circuit comprising a programmable memory cell array, said memory array comprising a plurality of segmented word lines and a plurality of bit lines, said word lines having an end-to-end resistance which is at least 10×

lower than that of the bit lines.

2. The integrated circuit of claim 1 wherein the memory array comprises a three-dimensional passive element memory cell array.

3. The integrated circuit of claim 2 comprising anti-fuse memory cells.

4. The integrated circuit of claim 2 comprising fuse memory cells.

5. The integrated circuit of claim 2 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

6. The integrated circuit of claim 1 wherein:

each word line comprises at least one word line segment on each of at least two word line layers that are connected together; and

each word line is operably coupled to an associated selected bias line traversing perpendicular to the word line segments.

7. The integrated circuit of claim 6 wherein each respective selected bias line is operably driven to a selected bias level by a respective first circuit arranged to initially drive the line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

8. The integrated circuit of claim 7 wherein the respective second circuit for each respective selected bias line comprises a plurality of spatially distributed circuits operably coupling the respective selected bias line to a source of the selected bias level.

9. The integrated circuit of claim 2 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

10. The integrated circuit of claim 9 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

11. The integrated circuit of claim 6 wherein the word line segments on a given word line layer in each array block are interleaved.

12. The integrated circuit of claim 11 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

13. A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 1.

14. An integrated circuit comprising a three-dimensional memory cell array, said array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, and further comprising a plurality of bit lines each at least 10×

greater in length than individual word line segments, each memory cell being read by driving an associated word line and sensing an associated bit line.

15. The integrated circuit of claim 14 further comprising at least three word line layers, wherein at least some segmented word lines comprise connected-together word line segments on a first group of one or more word line layers, and at least some segmented word lines comprise connected-together word line segments on a second group of one or more word line layers.

16. The integrated circuit of claim 14 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

17. The integrated circuit of claim 14 comprising anti-fuse memory cells.

18. The integrated circuit of claim 16 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

19. The integrated circuit of claim 16 wherein the word line segments on a given word line layer in each array block are interleaved.

20. The integrated circuit of claim 19 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

21. A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 14.