Word line arrangement having multi-layer word line segments for three-dimensional memory array
First Claim
1. An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line traversing perpendicular to the word line segments.
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Abstract
A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.
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Citations
36 Claims
- 1. An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line traversing perpendicular to the word line segments.
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18. A method for programming a three-dimensional passive element memory cell array, said method comprising the steps of:
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selecting a block of the memory array, each block comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each block further including a respective plurality of N selected bias lines traversing perpendicular to the word line segments;
selecting one of a plurality of select nodes of a multi-headed word line decoder circuit, each select node being coupled to a respective group of N word line driver circuits associated with the selected block, each word line driver circuit coupled to a respective one of the N selected bias lines for the selected block;
driving one of the N selected bias lines for the selected block to a selected bias level, thereby coupling a selected word line to a source of a suitable programming bias level; and
coupling a selected bit line in the selected block to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby program a selected memory cell coupled between the selected bit line and the selected word line. - View Dependent Claims (19, 20)
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- 21. An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line by a multi-headed decoder circuit, said decoder circuit comprising a plurality of select nodes routed on a layer beneath the memory array and coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.
Specification