Apparatus for thermal management of multiple core microprocessors

• US 20050180488A1
• Filed: 01/13/2005
• Published: 08/18/2005
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: Sony Corporation Of America (Sony Group Corp.)
• Original Assignee: Simon M. Tam, Stefan Rusu
• Inventors: Rusu, Stefan, Tam, Simon M.
• Granted Patent: US 7,144,152 B2
• Time in Patent Office: Days
• US Class Current: 374/141
• CPC Class Codes: G01K 1/026 arrangements for monitoring a plurality of temperatures, e.g. by multiplexing
• CPC Class Codes: G01K 7/42 Circuits effecting compensation of thermal inertia; Circuits for predicting the stationary value of a temperature
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus for managing the temperature of an integrated circuit having a multiple core microprocessor is described. Specifically, thermal sensors are placed at potential hot spots throughout each microprocessor core. A thermal management unit monitors the thermal sensors. If a thermal sensor identifies a hot spot, the thermal management unit adjusts the operating frequency and voltage of that microprocessor core accordingly.

Claims

1. An integrated circuit (IC) comprising:

m processor cores, wherein m is an integer greater than one, wherein each of the m processor cores has an operating frequency and an operating voltage;

n thermal sensors coupled to the m processor cores, wherein n is an integer greater than one, wherein the n thermal sensors provide signals representing the temperatures of the m processor cores;

a thermal management unit coupled to the n thermal sensors to monitor the temperatures of the n thermal sensors, and to adjust the operating frequencies and the operating voltages of the m processor cores based on the temperatures at each of the n thermal sensors.

2. The IC of claim 1, further comprising:

a cache memory coupled to the m processor cores.

3. The IC of claim 1, wherein the thermal management unit adjusts the operating frequency of one of the m processor cores if one of the n thermal sensors exceeds a predetermined temperature.

4. The IC of claim 1, wherein the thermal management unit adjusts the operating voltage of one of the m processor cores if one of the n thermal sensors exceeds a predetermined temperature.

5. The IC of claim 1, wherein the n thermal sensors are placed at potential hot spots on the m processor cores.

6. An apparatus comprising:

a temperature-to-voltage converter circuit which outputs a voltage dependent upon a sensed temperature of a processor; and

a ring oscillator coupled to the temperature-to-voltage converter circuit, wherein the ring oscillator generates a digital signal having a frequency which is a function of the sensed temperature.

7. The apparatus of claim 6, further comprising:

a level shifter coupled to the temperature-to-voltage converter circuit, wherein the level shifter reads the voltage output from the temperature-to-voltage converter circuit and generates a bias voltage.

8. The apparatus of claim 7, wherein the bias voltage generated by the level shifter biases the ring oscillator.

9. The apparatus of claim 8, wherein the ring oscillator comprises a plurality of inverters, wherein each of the plurality of inverters is coupled to a pull down transistor that biases the ring oscillator.

10. The apparatus of claim 6, wherein the digital signal frequency is proportional to the sensed temperature.

11. The apparatus of claim 10, wherein the digital signal frequency decreases if the sensed temperature increases.

12. The apparatus of claim 6, further comprising:

a counter to count a number of cycles of the digital signal over a period of time.

13. The apparatus of claim 12, further comprising:

a digital controller to compare the number of cycles of the digital signal to a reference value, wherein if the number of cycles is greater than the reference value, the operating frequency is decreased.

14. The apparatus of claim 13, wherein an operating frequency of the processor is increased if the number of cycles is less than the reference value.

15. The apparatus of claim 13, wherein an operating frequency is decreased, wherein the digital controller adjusts a phase locked loop (PLL), wherein the PLL provides a clock to the processor.

16. The apparatus of claim 15, wherein the digital controller adjusts a multiplying ratio of the PLL.

17. The apparatus of claim 15, wherein the digital controller adjusts an oscillator of the PLL.

18. (canceled)

19. (canceled)

20. (canceled)

21. (canceled)

22. (canceled)

23. (canceled)

24. (canceled)

25. (canceled)