Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

• US 20050180686A1
• Filed: 04/07/2005
• Published: 08/18/2005
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Patel, Satyadev R., Huibers, Andrew G., Chiang, Steve S.
• Granted Patent: US 7,671,428 B2
• Time in Patent Office: Days
• US Class Current: 385/18
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00214 Processes for the simultaneaous manufacturing of a network or an array of similar microstructural devices
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 1/00896 Temporary protection during separation into individual elements
• CPC Class Codes: B81C 1/00904 Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01054 : Xenon [Xe]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Claims

30. A wafer assembly comprising:

a lower semiconductor wafer comprising a plurality of mirror device areas, each mirror device area comprising a mirror array having mirrors disposed in a rectangular array area;

wherein the mirrors have mirror edges that are neither parallel nor perpendicular to edges of the rectangular array area;

an upper light transmissive wafer bonded in spaced apart relationship to the lower wafer; and

one or more intermediate wafers bonded between the upper and lower wafer and having open areas corresponding to each mirror device location.

1. A substrate assembly comprising:

a lower substrate comprising a plurality of mirror device areas, each mirror device area comprising a mirror array having a rectangular active area and a plurality of deflectable mirrors within the rectangular active area;

wherein the mirrors have a plurality of mirror edges that arc neither parallel nor perpendicular to the edges of the active area;

an upper light transmissive substrate bonded to the lower substrate with gaps therebetween; and

an intermediate substrate bonded between the upper and lower substrates and with open areas defining a plurality of cavities at each mirror device location in the gaps.

2. The substrate assembly of claim 1, further comprising a light blocking material on the light transmissive substrate.

3. The substrate assembly of claim 1, wherein each mirror device comprises a plurality of micromirrors, a getter, a lubricant and a light blocking mask, and wherein the mirrors are square in shape having no mirror edges parallel or perpendicular to the edges of the active area.

4. The substrate assembly of claim 2, wherein the light blocking material is provided as a rectangular mask at each minor device location.

5. The substrate assembly of claim 1, wherein the upper and lower substrates have score or partial saw lines in horizontal and vertical directions.

6. The substrate assembly of claim 1, wherein the score or partial saw lines are from 50 to 95% of the thickness of the substrate.

7. The substrate assembly of claim 3, wherein the micromirrors comprises mirror elements and hinges that are positioned separated from and parallel to the mirror elements in different planes.

8. The substrate assembly of claim 1, wherein the substrates are bonded together with an adhesive.

9. The substrate assembly of claim 8, wherein the adhesive is an epoxy.

10. The substrate assembly of claim 5, wherein the score or partial saw lines on the upper and lower substrates are offset from each other.

11. The substrate assembly of claim 1, wherein the mirror devices comprise a getter within the cavity at each mirror device location.

12. The substrate assembly of claim 1, wherein the mirror devices comprise a lubricant within the cavity at each mirror device location.

13. The substrate assembly of claim 1, wherein the lower substrate is held on a lower packaging substrate.

14. The substrate assembly of claim 13, wherein a distance between the upper and lower substrates is from 1 to 100 microns.

15. The substrate assembly of claim 11, wherein the getter is a moisture, particle or hydrogen getter.

16. The substrate assembly of claim 1, wherein a group of the mirror edges of the mirrors is neither parallel nor perpendicular to the edges of the active area, and another group of the edges is parallel to active area edges.

17. The substrate assembly of claim 1, wherein the mirror edges are approximately 45 degrees relative to the active area edges.

18. The substrate assembly of claim 1, wherein no mirror edges are parallel or perpendicular to edges of the active area.

19. The substrate assembly of claim 18, wherein each mirror has a switching axis that is at a non-parallel and non-perpendicular angle to at least one edge of the mirror.

20. The substrate assembly of claim 1, wherein each mirror has a switching axis parallel to at least one edge of the active area.

21. The substrate assembly of claim 20, wherein each mirror has a switching axis at an angle of from 40 to 55 degrees to one or more edges of each mirror.

22. The substrate assembly of claim 1, wherein each mirror has a front edge that is non-perpendicular to any edge of the active area.

23. The substrate assembly of claim 1, wherein each mirror is a square mirror having four edges defining the square mirror, wherein the four edges of each mirror is neither parallel nor perpendicular to any edges of the active area.

24. The substrate assembly of claim 23, wherein addressing rows connect to every other mirror.

25. The substrate assembly of claim 23, wherein addressing columns connect to every other mirror.

26. The substrate assembly of claim 23, wherein hinges are disposed below each mirror and are held on support posts.

27. The substrate assembly of claim 1I, wherein the mirrors comprise hinges that extend parallel to the leading and trailing edges of the active area.

28. The substrate assembly of claim 1, wherein the mirrors have jagged edges.

29. The substrate assembly of claim 11, wherein the getter is a moisture getter.

31. The wafer assembly of claim 30, wherein a group of the mirror edges of the mirrors is neither parallel nor perpendicular to the edges of the rectangular array area, and another group of the edges is parallel to rectangular array area edges.

32. The wafer assembly of claim 30, wherein no mirror edges are parallel or perpendicular to edges of the rectangular array area.

33. The wafer assembly of claim 32, wherein each mirror has a switching axis that is at a non-parallel and non-perpendicular angle to at least one edge of the mirror.

34. The wafer assembly of claim 30, wherein each mirror has a switching axis parallel to at least one edge of the active area.

35. The wafer assembly of claim 34, wherein each mirror has a switching axis at an angle of from 40 to 55 degrees to one or more edges of each mirror.

36. The wafer assembly of claim 30, wherein each mirror has a front edge that is non-perpendicular to any edge of the active area.

37. The wafer assembly of claim 30, wherein each mirror is a square mirror having four edges defining the square mirror, wherein the four edges of each mirror is neither parallel nor perpendicular to any edges of the active area.

38. The wafer assembly of claim 30, wherein addressing rows connect to every other mirror.

39. The wafer assembly of claim 30, wherein addressing columns connect to every other mirror.

40. The wafer assembly of claim 30, wherein hinges are disposed below each mirror and are held on support posts.

41. The wafer assembly of claim 34, wherein the mirrors comprise hinges that extend parallel to the leading and trailing edges of the active area.

42. The wafer assembly of claim 30, wherein the mirrors have jagged edges.

43. The wafer assembly of claim 30, wherein the mirrors are bonded together with an adhesive.

44. The wafer assembly of claim 43, wherein the adhesive is an epoxy.

45. The wafer assembly of claim 30, further comprising a light blocking material on the upper wafer.

46. The wafer assembly of claim 30, wherein the light blocking material is provided as a rectangular mask at each mirror array device location.

47. The wafer assembly of claim 30, wherein the mirror devices comprise a stiction treatment.

48. The wafer assembly of claim 30, further comprising horizontal and vertical '"'"'score or partial saw lines.

49. The wafer assembly of claim 48, wherein the score or partial saw lines arc offset from each other at least in one of the horizontal or vertical directions.

50. The wafer assembly of claim 30, wherein the mirror devices on the lower wafer comprise circuitry and micromechanical structures formed monolithically on the same substrate.

51. The wafer assembly of claim 50, further comprising areas of lubricant.

52. The wafer assembly of claim 50, further comprising getter material in each cavity.

53. The wafer assembly of claim 30, wherein one or more of a mask lubricant or getter is present on the upper wafer.

54. The wafer assembly of claim 52, wherein the getter is a moisture getter.

31-1. The wafer assembly of claim 30, wherein the mirror edges are approximately 45 degrees relative to the rectangular array area edges.