Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

• US 20050181532A1
• Filed: 04/07/2005
• Published: 08/18/2005
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Patel, Satyadev R., Huibers, Andrew G., Chiang, Steve S.
• Granted Patent: US 7,655,492 B2
• Time in Patent Office: Days
• US Class Current: 438/66
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00214 Processes for the simultaneaous manufacturing of a network or an array of similar microstructural devices
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 1/00896 Temporary protection during separation into individual elements
• CPC Class Codes: B81C 1/00904 Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01054 : Xenon [Xe]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Claims

1. A method for making a plurality of spatial light modulator, comprising:

providing a transparent wafer and a semiconductor wafer;

forming a plurality of micromirrors within a plurality of rectangular micromirror arrays on the semiconductor wafer;

wherein the mirrors are formed on semiconductor wafer in a rectangular array area, and wherein the mirrors have mirror edges that are neither parallel nor perpendicular to edges of the rectangular array area;

bonding the transparent wafer and semiconductor wafer together with a spacer layer therebetween so as to form gaps in which the micromirrors of the micromirror arrays are disposed;

wherein the bonding is performed by an application of an adhesive, an application of pressure to press the transparent wafer and semiconductor wafer together, and a step of curing the adhesive so as to form a wafer assembly; and

singulating the wafer assembly into individual spatial light modulators.

2. The method of claim 1, wherein a group of the mirror edges of the mirrors is neither parallel nor perpendicular to the edges of the rectangular array area, and another group of the edges is parallel to rectangular array area edges.

3. The method of claim 1, wherein the mirror edges are approximately 45 degrees relative to the rectangular array area edges.

4. The method of claim 1, wherein no mirror edges are parallel or perpendicular to edges of the rectangular array area.

5. The method of claim 4, wherein each mirror has a switching axis that is at a non-parallel and non-perpendicular angle to at least one edge of the mirror.

6. The method of claim 1, wherein each mirror has a switching axis parallel to at least one edge of the active area.

7. The method of claim 5, wherein each mirror has a switching axis at an angle of from 40 to 55 degrees to one or more edges of each mirror.

8. The method of claim 1, wherein each mirror has a front edge that is non-perpendicular to any edge of the active area.

9. The method of claim 1, wherein each mirror is a square mirror having four edges defining the square mirror, wherein the four edges of each mirror is neither parallel nor perpendicular to any edges of the active area.

10. The method of claim 1, wherein addressing rows connect to every other mirror.

11. The method of claim 1, wherein addressing columns connect to every other mirror.

12. The method of claim 1, wherein hinges are disposed below each mirror and are held on support posts.

13. The method of claim 5, wherein the mirrors comprise hinges that extend parallel to the leading and trailing edges of the active area.

14. The method of claim 1, wherein the mirrors have jagged edges.

15. The method of claim 1, wherein the mirrors have square mirror plates that have no edges parallel or perpendicular to the edges of the rectangular array area, and wherein the cavity comprises a getter and a lubricant.

16. The method of claim 9, further comprising providing a getter for each micromirror array before bonding the transparent wafer to the semiconductor wafer.

17. The method of claim 16, further comprising providing a light blocking mask on the transparent wafer.

18. The method of claim 17, wherein when the wafer assembly is singulated into individual spatial light modulators, a light blocking mask is disposed on a transparent substrate within each spatial light modulator.

19. The method of claim 18, wherein the light blocking mask is formed as a rectangular flame around each micromirror array in each spatial light modulator after singulation.

20. The method of claim 19, wherein a stiction reducing agent is provided after wafer bonding.

21. The method of claim 20, wherein each spatial light modulator comprises a getter, stiction reducing agent and light blocking mask.

22. The method of claim 21, wherein singulation is performed such that an edge of the transparent substrate in each spatial light modulator is offset from an edge of the semiconductor substrate in each spatial light modulator.

23. The method of claim 22, wherein the transparent wafer is glass.

24. The method of claim 23, wherein the semiconductor wafer is silicon.

25. The method of claim 24, further comprising a packaging substrate, wherein the silicon substrate of each spatial light modulator is disposed on a corresponding packaging substrate.

26. The method of claim 25, wherein the offset edges of the glass and silicon substrates in each spatial light modulator results in an exposed area on the silicon substrate for testing.

27. The method of claim 26, wherein the exposed area further comprises bond wires bonded thereto.

28. The method of claim 27, wherein the spacer layer comprises one or more intermediate wafers with open areas bonded between the transparent wafer and the semiconductor wafer.

29. The method of claim 28, wherein the semiconductor substrate and the transparent substrate are aligned and pressed in a press.

30. The method of claim 29, wherein the adhesive is an epoxy.

31. The method of claim 30, wherein the epoxy is a UV cure epoxy.

32. The method of claim 30, wherein the number of micromirrors in each micromirror army is from 6,000 to about 6 million.

33. The method of claim 32, wherein the wafer assembly is singulated into individual spatial light modulators by scribing and breaking.

34. The method of claim 32, wherein the singulation of the wafer assembly into individual spatial light modulators comprises sawing.

35. The method of claim 32, wherein the singulation of the wafer assembly comprises sawing partially through each wafer followed by breaking along the sawed lines.

36. The method of claim 35, wherein the sawing is done in the presence of a high-pressure jet of water.

37. The method of claim 32, wherein the transparent wafer and semiconductor wafer are bonded together with the gap therebetween being from 1 to 250 microns.

38. The method of claim 32, wherein the getter is a moisture getter.

39. The method of claim 32, wherein the getter is a particle getter.

40. The method of claim 32, wherein the getter is a combination getter.