Controller for controlling nonvolatile memory

• US 20050182893A1
• Filed: 01/12/2005
• Published: 08/18/2005
• Est. Priority Date: 02/16/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Suh, Woon-Sik
• Granted Patent: US 7,373,452 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: Y02E 10/20 Hydro energy

Abstract

A memory controller is provided which is connected to a nonvolatile memory (e.g., a NAND flash memory) and a volatile memory (e.g., a DRAM or SDRAM), where the memory controller controls an access to the nonvolatile memory and the volatile memory in response to a memory request, and includes a memory for storing address information of data stored in the volatile memory, and where the memory controller determines whether address information inputted at the memory request is identical to address information of the memory, and selectively accesses the nonvolatile memory according to the determined result.

Claims

1. A memory system comprising:

a NAND flash memory;

a RAM in signal communication with the NAND flash memory for storing data of the NAND flash memory; and

a controller in signal communication with the NAND flash memory for controlling an access to the RAM and the NAND flash memory in response to a memory request,

wherein the controller includes a memory for storing address information of the data stored in the RAM, and controls the NAND flash memory to be selectively accessed at the memory request with reference to the address information of the memory.

2. The memory system of claim 1, wherein the controller determines whether address information inputted at the memory request is identical to the address information of the memory, and selectively accesses the NAND flash memory according to the determined result.

3. The memory system of claim 2, wherein when the address information inputted at the memory request is identical to the address information of the memory, the controller outputs the data of the RAM to the outside without any access to the NAND flash memory.

4. The memory system of claim 2, wherein when the address information inputted at the memory request is not identical to the memory address information, the controller controls the NAND flash memory to output the data of the NAND flash memory to the RAM and the outside.

5. The memory system of claim 1, wherein the controller manages the NAND flash memory in units of pages instead of blocks and stores page address information of the NAND flash memory in the memory.

6. The memory system of claim 1, wherein whenever externally-inputted data is stored in the RAM, the controller stores address information of the stored data in the memory.

7. The memory system of claim 2, the controller further comprising:

a main control unit for issuing a read/write access command according to whether the address information inputted at the memory request is identical to the address information of the memory;

a memory control unit in signal communication with the main control unit for controlling an access operation of the RAM in response to the read/write access command from the main control unit when the address information inputted at the memory request is identical to the memory address information; and

a flash memory management and control unit in signal communication with the main control unit for controlling an access operation of the NAND flash memory in response to the read/write access command from the main control unit when the address information inputted at the memory request is not identical to the memory address information.

8. The memory system of claim 7, wherein when the address information inputted at the memory request is identical to the memory address information, the main control unit converts the address to a RAM address suitable for the RAM, and outputs the converted RAM address to the RAM.

9. The memory system of claim 7, wherein when the address information inputted at the memory request is not identical to the memory address information, the flash memory management and control unit converts the address to a NAND address suitable for the NAND flash memory.

10. The memory system of claim 7, wherein the flash memory management and control unit stores related information on an accessed page of the NAND flash memory in the memory.

13. The memory system of claim 7, wherein when the new data is written in the RAM, the main control unit stores in the memory valid address information for indicating whether new data is stored in the RAM.

14. The memory system of claim 13, wherein when an update operation is requested, the flash memory management and control unit generates a NAND address with reference to the valid address information of the memory.

15. The memory system of claim 1, wherein the controller further includes a temporary memory that temporarily stores data read from the NAND flash memory.

16. The memory system of claim 15, wherein when the data of the RAM is stored in the NAND flash memory, the temporary memory stores data from the RAM by the control of the memory control unit, the stored data being outputted to the NAND flash memory by the control of the flash memory management and control unit.

17. The memory system of claim 15, wherein when the data of the NAND flash memory is stored in the RAM, the temporary memory stores data from the NAND flash memory by the control of the flash memory management and control unit, the stored data being outputted to the RAM and the outside by the control of the memory control unit.

11. The memory system 10, wherein the flash memory management and control unit stores defective page information in the memory when the accessed page of the NAND flash memory is a defective page.

12. The memory system of claim 11, wherein the flash memory management and control unit includes a page address table that is set to select another page instead of the defective page when the NAND flash memory is accessed.

18. A memory system comprising:

a NAND flash memory;

a RAM for storing data of the NAND flash memory; and

a controller in signal communication with the NAND flash memory and the RAM for controlling an access to the RAM and the NAND flash memory,

wherein the controller comprises;

a memory for storing a tag address from memory address information of data stored in the RAM;

a main control unit in signal communication with the memory for issuing either one of first and second access commands according to whether a tag address from a memory address inputted at a memory request is identical to a tag address of the memory;

a memory control unit in signal communication with the main control unit for controlling an access to the RAM in response to the first access command; and

a flash memory management and control unit in signal communication with the main control unit for controlling an access to the NAND flash memory in response to the second access command.

19. The memory system of claim 18, wherein when the tag address from the memory address inputted at the memory request is identical to the tag address of the memory, the controller controls the memory control unit to output data of the RAM to the outside without an access to the NAND flash memory.

20. The memory system of claim 18, wherein when the tag address from the memory addresses inputted at the memory request is not identical to the tag address of the memory, the controller controls the flash memory management and control unit and the memory control unit to output data of the NAND flash memory to the RAM and to the outside.

21. The memory system of claim 18, wherein the flash memory management and control unit manages the NAND flash memory in units of not blocks but pages, and stores the page address information of the NAND flash memory in the memory.

22. The memory system of claim 18, wherein the main control unit stores a tag address of the stored data in the memory whenever an externally inputted data is stored in the RAM.

23. The memory system of claim 18, wherein when the tag address from the memory addresses inputted at the memory request is identical to the tag address of the memory, the main control unit converts the memory address to the RAM address suitable for the RAM, and outputs the converted RAM address to the RAM.

24. The memory system of claim 23, wherein when the tag address from the memory addresses inputted at the memory request is not identical to the tag address of the memory, the flash memory management and control unit converts the memory address to the NAND address suitable for the NAND flash memory.

25. The memory system of claim 18, wherein the flash memory management and control unit stores information related on an accessed page of the NAND flash memory in the memory.

26. The memory system of claim 25, wherein the flash memory management and control unit stores defective page information in the memory when the accessed page of the NAND flash memory is a defective page.

27. The memory system of claim 25, wherein the flash memory management and control unit includes a page address table that is set to select another page instead of the defective page when the NAND flash memory is accessed.

28. The memory system of claim 18, wherein when new data is written in the RAM, the main control unit stores valid address information for indicating whether the new data is stored in the RAM.

29. The memory system of claim 28, wherein when an update operation is requested, the flash memory management and control unit generates a NAND address with reference to the valid address information of the memory.

30. The memory system of claim 18, wherein the controller further comprises a temporary memory in signal communication with the memory control unit that temporarily stores data read from the NAND flash memory.

31. The memory system of claim 30, wherein when data from the RAM is stored in the NAND flash memory, the temporary memory stores data from the RAM by the control of the memory control unit, the stored data being outputted to the NAND flash memory according to the flash memory management and control unit.

32. The memory system of claim 30, wherein when data from the NAND flash memory is stored in the RAM, the temporary memory stores data from the NAND flash memory by the control of the flash memory management and control unit, the stored data being outputted to the RAM and to the outside by a control of the memory control unit.