Electronic data processing device

• US 20050182961A1
• Filed: 12/06/2004
• Published: 08/18/2005
• Est. Priority Date: 12/12/2003
• Status: Active Grant

• Current Assignee: ATOS Worldline SA (Atos SE)
• Original Assignee: ATOS Worldline SA (Atos SE)
• Inventors: Moons, Marc, Himbeeck, Carl Van, Timmermans, Peter
• Granted Patent: US 7,454,629 B2
• Time in Patent Office: Days
• US Class Current: 726/26
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

An electronic data processing device, comprising an access protected memory, provided for storing secure data and a data processing member, provided for processing said secure data, said terminal comprises a tampering detection and protection circuit provided for detecting a tamper condition and for generating a tamper signal upon detection of said tamper condition, said tampering detection and protection circuit being connected to a tampering sequencer, provided for disabling said processing member upon receipt of said tampering signal, said memory comprises a security register provided for storing keys for encrypting said secure data and a memory section provided for storing keys for encrypting said secure data and a memory section provided for temporarily storing secure data processed by said data processing member, said tampering sequencer comprises an internal clock generator provided for generating, upon receipt of said tamper signal a tamper pulse and a series of clock pulses, said tampering sequencer being provided for erasing under control of said tamper pulse, said security data stored in said security register and for erasing, under control of said series of clock pulses said processed secure data stored in said memory section.

Claims

1. An electronic data processing device, comprising an access protected memory, provided for storing secure data, in particular data related to a fund transfer, and a data processing member connected to said memory via a bus and provided for processing said secure data, said terminal comprises a tampering detection and protection circuit connected to said bus and provided for detecting a tamper condition and for generating a tamper signal upon detection of said tamper condition, said tampering detection and protection circuit being connected to a tampering sequencer, provided for disabling said processing member upon receipt of said tampering signal, characterised in that said memory comprises a security register provided for storing keys for encrypting said secure data and a memory section provided for temporarily storing secure data processed by said data processing member, said tampering sequencer comprises an internal clock generator provided for generating, upon receipt of said tamper signal a tamper pulse and a series of clock pulses, said tampering sequencer being provided for erasing under control of said tamper pulse, said security data stored in said security register and for erasing, under control of said series of clock pulses said processed secure data stored in said memory section.

2. An electronic data processing device as claimed in claim 1, characterised in that said tampering sequencer is provided for generating said tamper pulse asynchronously with respect to said series of clock pulses.

3. An electronic data processing device as claimed in claim 1, characterised in that said tamper pulse has a duration of at most 1 msec.

4. An electronic data processing device as claimed in claim 1, characterised in that said tampering detection and protection circuit is provided for detecting a plurality of tamper conditions and for assigning to each tamper condition an identifying code, identifying the detected tamper condition, said tampering sequencer being provided with tampering recognition means, provided for recognising, based on said identifying code, each of said tamper conditions and for attributing a tampering condition priority level to each of said tamper conditions, said tamper condition priority level being selected among a set o priority levels comprising at least a first and a second level value, said tampering sequencer being provided for receiving said tampering condition priority level and for generating said tamper pulse and said series of clock pulses immediately upon receipt of said first level value and for upholding said generation of said tamper pulse and said series of clock pulses for a predetermined time period, upon receipt of said second level value.

5. An electronic data processing device as claimed in claim 4, characterised in that said tampering detection and protection circuit is provided with a tampering request generator provided for generating a request signal when said predetermined time period has lapsed, said tampering detection and protection circuit being further provided for verifying, under control of said request signal, if the tamper condition, having caused the tamper signal generation, still remains and for generating an enabling signal if said tamper condition remains and a disabling signal if said tampering condition did not remain, said tampering sequencer being provided for disabling said generation of said upheld tampering pulse and clock pulses under control of said disabling signal and for enabling said generation of said upheld tamper pulse and clock pulses under control of said enabling signal.

6. An electronic data processing device as claimed in claim 1, characterised in that said tampering detection and protection circuit is provided for disconnecting, under control of said series of clock pulses, said memory section from said bus before erasing said secure data.

7. An electronic data processing device as claimed in claim 1, characterised in that said series of clock pulses have a frequency situated in a range between 1 and 10 MHz.

8. An electronic data transfer terminal as claimed in claim 1, characterised in that said tamper processing circuit is provided for disabling any access to said memory as long as said tampering signal remains active.

9. An electronic data processing device as claimed in claim 1 characterised in that said tampering detection and protection circuit comprises a register provided for storing tampering status data.

10. An electronic data processing device as claimed in claim 1, characterised in that said tampering detection and protection circuit is provided for being powered by an autonomous power supply source, independent of the one powering the data processing member.

11. An electronic data processing device as claimed in claim 1, characterised in that said series of clock pulses have a frequency of 5 MHz.