Performance counters in a multi-threaded processor

• US 20050183065A1
• Filed: 02/13/2004
• Published: 08/18/2005
• Est. Priority Date: 02/13/2004
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Wolczko, Mario I., Talcott, Adam R.
• Application Number:
  US10/779,216
• Publication Number:
  US 20050183065A1
• Time in Patent Office: Days
• US Class Current: 717/124
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A method of performance counting within a multi-threaded processor. The method includes counting events within the processor to provide an event count, and attributing the event count to events occurring within a thread of the processor or to events occurring globally within the processor.

Claims

1. A method of performance counting within a multi-threaded processor comprising:

counting events within the processor to provide an event count; and

attributing the event count to events occurring within a thread of the processor or to events occurring globally within the processor.

2. The method of claim 1 further comprising:

binding counters to a thread.

3. The method of claim 2 further comprising:

starting and stopping the counters bound to the thread independently of any other counters.

4. The method of claim 1 further comprising:

globally starting and stopping the counters for all events being counted.

5. The method of claim 1 further comprising:

partitioning the counters among a plurality of threads of the processor.

6. The method of claim 1 further comprising:

determining whether a particular thread receives an overflow interrupt.

7. A method of performance counting within a multi-threaded processor comprising:

counting a plurality of events within the processor via a plurality of counters to provide a respective plurality of event counts;

assigning at least one counter to a thread; and

enabling the thread to start and stop all counters assigned to the thread.

8. The method of claim 7 further comprising:

enabling the thread to globally start and stop all of the plurality of counters.

9. A method of performance counting within a multi-threaded processor comprising:

counting a plurality of events within the processor to provide respective plurality of event counts via a respective plurality of counters; and

,

partitioning the plurality of counters among multiple threads of the processor.

10. A method of performance counting within a multi-threaded processor comprising:

counting a plurality of events within the processor to provide respective plurality of event counts via a respective plurality of counters;

assigning a first counter to a thread;

assigning a second counter to another thread; and

determining which thread receives an overflow interrupt based upon when one of the first and second counters overflows.

11. An apparatus for performance counting within a multi-threaded processor comprising:

means for counting events within the processor to provide an event count; and

means for attributing the event count to events occurring within a thread of the processor or to events occurring globally within the processor.

12. The apparatus of claim 11 further comprising:

means for binding counters to a thread.

13. The apparatus of claim 11 further comprising:

means for starting and stopping the counters bound to the thread independently of any other counters.

14. The apparatus of claim 11 further comprising:

means to globally starting and stopping the counters for all events being counted.

15. The apparatus of claim 11 further comprising:

means for partitioning the counters among a plurality of threads of the processor.

16. The apparatus of claim 11 further comprising:

means for determining whether a particular thread receives an overflow interrupt.

21. The performance counter of claim 11 wherein:

the counter module indicates whether a particular thread receives an overflow interrupt.

17. A performance counter for counting events within a multi-threaded processor comprising:

a counter module, the counter module counting events within the processor to provide an event count; and

an attribution module, the attribution module attributing the event count to events occurring within a thread of the processor or to events occurring globally within the processor.

18. The performance counter of claim 17 further comprising:

a counter control module, the counter control module enabling the thread to start and stop the counting for events attributed to the thread.

19. The performance counter of claim 17 wherein:

the counter control module enables the thread to globally start and stop the counting of all events.

20. The performance counter of claim 17 wherein:

the counter module includes a plurality of counters; and

,

the counters may be partitioned among a plurality of threads of the processor.