Method for aligning capacitor plates in a security tag and a capacitor formed thereby

• US 20050183264A1
• Filed: 11/29/2004
• Published: 08/25/2005
• Est. Priority Date: 02/23/2004
• Status: Active Grant

• Current Assignee: CHECKPOINT SYSTEMS, INC. (CCL Industries Incorporated)
• Original Assignee: CHECKPOINT SYSTEMS, INC. (CCL Industries Incorporated)
• Inventors: Cote, Andre, Eckstein, Eric
• Granted Patent: US 7,119,685 B2
• Time in Patent Office: Days
• US Class Current: 29/834
• CPC Class Codes: G01V 15/00 Tags attached to, or associated with, an object, in order to enable detection of the object record carriers for use with machines having a detectable tag or marker G06K19/00
• CPC Class Codes: G06K 19/07718 the record carrier being manufactured in a continuous process, e.g. using endless rolls
• CPC Class Codes: G06K 19/07786 the antenna being of the HF type, such as a dipole
• CPC Class Codes: H01G 13/00 Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 9/265 Open ring dipoles; Circular dipoles
• CPC Class Codes: H01Q 9/285 Planar dipole H01Q9/065 takes precedence; patch antenna H01Q9/0407
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 3/041 by using a die for cutting the conductive material
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49133 with component orienting
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A circuit element the presence of the circuit element includes first and second capacitor plates disposed over the surface of the substrate in an aligned relationship with each other. The aligned relationship has manufacturing variations in the relative positioning of the first and second capacitor plates and a dielectric layer disposed between the first and second capacitor plates. At least one of the first and second capacitor plates is formed substantially smaller relative to the other of the first and second capacitor plates. The at least one of the capacitor plates is disposed at a predetermined offset in at least one planar direction from an edge of the other of the first and second capacitor plates. The predetermined offset is selected according to the manufacturing variations to prevent variations in the value of capacitance of the capacitor due to the manufacturing variations.

Claims

1. A circuit element disposed on a substrate surface to reflect electromagnetic energy for the purpose of indicating the presence of said circuit element, comprising:

a. first and second capacitor plates disposed over said surface of said substrate in an aligned relationship with each other, said aligned relationship having manufacturing variations in the relative positioning of said first and second capacitor plates;

b. a dielectric layer disposed between said first and second capacitor plates;

c. at least one of said first and second capacitor plates being formed substantially smaller relative to the other of said first and second capacitor plates; and

d. said at least one of said first and second capacitor plates being disposed at a predetermined offset in at least one planar direction from an edge of the other of said first and second capacitor plates, said predetermined offset being selected in accordance with said manufacturing variations to prevent variations in the value of capacitance of said capacitor due to said manufacturing variations.

2. The circuit element of claim 1, wherein said at least one capacitor plate of said first and second capacitor plates is disposed over said other capacitor plate of said first and second capacitor plates.

3. The circuit element of claim 1, wherein said other capacitor plate of said first and second capacitor plates is disposed over said at least one capacitor plate of said first and second capacitor plates.

4. The circuit element of claim 1, wherein said dielectric layer comprises said substrate whereby said first and second capacitor plates are disposed on opposing sides of said substrate.

5. The circuit element of claim 1, wherein said at least one capacitor plate of said first and second capacitor plates is disposed at a predetermined offset from two edges of the other capacitor plate of said first and second capacitor plates in two orthogonal planar directions.

6. The circuit element of claim 1, comprising the step of selecting the magnitude of said predetermined offset is selected to provide an alignment of said first and second capacitor plates wherein the entire surface area of said at least one capacitor plate of said first and second capacitor plates faces an opposing surface area of the other capacitor plate of said first and second capacitor plates regardless of said manufacturing variations.