Semiconductor device gate structure and method of forming the same

• US 20050184348A1
• Filed: 02/15/2005
• Published: 08/25/2005
• Est. Priority Date: 02/19/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Choong-Ho, Park, Dong-Gun, Lee, Chul, Yoshida, Makoto, Youn, Jae-Man
• Application Number:
  US11/059,145
• Publication Number:
  US 20050184348A1
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, and a first conductive pattern extends from a lower portion of the channel pattern in a first direction verticalperpendicular to the channel pattern and in parallel with the substrate. A second conductive pattern extends from an upper portion of the channel pattern in a second direction verticalperpendicular to the channel pattern and in parallel with the substrate. Accordingly, the channel length of the MOS transistor is determined by a distance between the first and second conductive patterns, and a channel width of the MOS transistor is determined by a diameter of the gate structure. Short channel and narrow width effects are sufficiently prevented in a MOS transistor.

Claims

1. A gate structure, comprising:

a gate electrode formed on a substrate, the gate electrode including a conductive material; and

a gate insulation layer enclosing a side surface of the gate electrode.

2. The gate structure of claim 1, wherein the gate electrode has a pillar shape protruded from the substrate in a vertical direction.

3. The gate structure of claim 2, wherein the gate insulation layer has a pillar ring shape, and makes contact with the side surface of the gate electrode.

4. The gate structure of claim 2, wherein the gate insulation layer has a cylindrical shape, and makes contact with the side surface and a bottom surface of the gate electrode.

5. The gate structure of claim 1, wherein the gate electrode includes a first pillar having a first diameter and a second pillar that is formed on a top surface of the first pillar and has a second diameter greater than the first diameter, and the first and second pillars are integrally formed with each other.

6. The gate structure of claim 5, wherein the gate insulation layer is formed on a side surface and a bottom surface of the first pillar and on a bottom surface of the second pillar.

7. The gate structure of claim 1, wherein the substrate includes a recessed portion on a top surface thereof, and a lower portion of the gate electrode is formed in the recessed portion.

8. The gate structure of claim 1, wherein the gate electrode comprises a polysilicon layer doped with impurities.

9. The gate structure of claim 8, wherein the gate electrode includes a metal silicide layer on a top surface of the polysilicon layer.

10. The gate structure of claim 9, wherein the metal silicide layer comprises at least one selected from the group consisting of tungsten silicide, titanium silicide, tantalum silicide, cobalt silicide, and nickel silicide.

11. The gate structure of claim 1, wherein the gate electrode includes a conductive pattern on an inner side surface of the gate electrode and a metal silicide plug filling an inside of the conductive pattern, and the conductive pattern includes doped polysilicon with impurities.

12. The gate structure of claim 1, wherein the gate electrode comprises at least one selected from the group consisting of tungsten, titanium, tantalum, cobalt, nickel, molybdenum, and ruthenium.

13. The gate structure of claim 1, wherein the gate insulation layer includes at least one selected from the group consisting of a silicon oxide (Si_xO_y, wherein x and y are positive numbers) layer, a silicon oxynitride (SiON) layer, a tantalum oxide (Ta₂O₅) layer, a tantalum oxynitride (TaON) layer, a titanium oxide (TiO₂) layer, an aluminum oxide (Al₂O₃) layer, a yttrium oxide (Y₂O₃) layer, a zirconium oxide (ZrO₂) layer, a hafnium oxide (HfO₂) layer, a barium titanate oxide (BaTiO₃) layer, a strontium titanate oxide (SrTiO₃)layer and combinations thereof.

14. A semiconductor device comprising:

a gate structure including a gate electrode formed on a substrate, and a gate insulation layer enclosing a side surface of the gate electrode;

a channel pattern covering a surface of the gate insulation layer;

a first conductive pattern extending from a lower portion of the channel pattern; and

a second conductive pattern extending from an upper portion of the channel pattern.

15. The semiconductor device of claim 14, wherein the gate electrode has a pillar shape protruded from the substrate in a vertical direction, and the gate insulation layer has a pillar ring shape that makes contact with the side surface of the gate electrode.

16. The semiconductor device of claim 14, wherein the channel pattern has a pillar ring shape, the gate insulation layer is formed on an inner side surface of the channel pattern, and the gate electrode has a pillar shape that makes contact with an inner side surface of the gate insulation layer.

17. The semiconductor device of claim 14, wherein the channel pattern has a cylindrical shape including inner and outer side surfaces and an open top portion, the gate electrode having a pillar shape is received in the channel pattern, and the gate insulation layer is formed between the channel pattern and the gate electrode, so that the gate insulation layer makes contact with both of the gate electrode and the channel pattern.

18. The semiconductor device of claim 14, wherein the channel pattern includes single-crystalline silicon formed by an epitaxial process.

19. The semiconductor device of claim 18, wherein the channel pattern includes impurities doped by an in-situ process during the epitaxial process.

20. The semiconductor device of claim 14, wherein the first and the second conductive patterns cover lower and upper portions of the channel pattern, respectively.

21. The semiconductor device of claim 14, wherein the first and the second conductive patterns extend in different directions from each other.

22. The semiconductor device of claim 14, wherein the first and the second conductive patterns extend in a horizontal direction from the gate structure.

23. The semiconductor device of claim 14, wherein the first and the second conductive patterns horizontally extend from the gate structure in a same direction, respectively, and the first conductive pattern is longer than the second conductive pattern.

24. The semiconductor device of claim 14, wherein the first and the second conductive patterns comprise doped single-crystalline silicon formed by an epitaxial process and an impurity doping process.

25. The semiconductor device of claim 14, wherein the substrate has a recessed portion on a top surface thereof, and a lower portion of the gate structure is formed in the recessed portion.

26. The semiconductor device of claim 14, wherein the first conductive pattern is formed on a surface of the substrate.

27. The semiconductor device of claim 14, wherein the substrate includes an impurity doped region at a surface portion thereof.

28. The semiconductor device of claim 14, wherein the first conductive pattern is spaced apart from the substrate by a predetermined distance.

29. The semiconductor device of claim 14, further comprising an insulation interlayer between the first conductive pattern and a surface of the substrate.

30. The semiconductor device of claim 14, wherein the substrate includes an impurity doped region at a surface portion thereof.

31. A semiconductor device comprising:

a gate structure including a gate electrode having a pillar shape extending from a substrate in a vertical direction, and a gate insulation layer enclosing a side surface of the gate electrode;

a channel pattern comprising single-crystalline silicon grown by an epitaxial process and having a cylindrical shape including inner and outer side surfaces, the inner side surface of the channel pattern making contact with a surface of the gate insulation layer;

a first conductive pattern enclosing the outer side surface of the channel pattern at a lower portion thereof and extending in a first direction perpendicular to the channel pattern; and

a second conductive pattern enclosing the outer side surface of the channel pattern at an upper portion thereof and extending in a second direction perpendicular to the channel pattern.

32. The semiconductor device of claim 31, wherein the first and the second conductive patterns are doped with impurities.

33. The semiconductor device of claim 31, wherein the channel pattern has a thickness of about 100 Å

to about 300 Å

.

34. The semiconductor device of claim 31, further comprising an insulation interlayer between the first and second conductive patterns, so that the insulation interlayer covers the channel pattern.

35. The semiconductor device of claim 31, wherein the gate electrode includes a first pillar having a first diameter and a second pillar that is formed on a top surface of the first pillar and has a second diameter greater than the first diameter, the first and second pillars being integrally formed with each other.

36. The semiconductor device of claim 35, wherein the channel pattern covers the first pillar.

37. The semiconductor device of claim 36, wherein the gate insulation layer is formed between the first pillar and the channel pattern and between the second pillar and the channel pattern.

38. The semiconductor device of claim 36, further comprising a capping layer enclosing the second pillar.

39. The semiconductor device of claim 38, wherein the gate insulation layer is formed between the gate electrode and the channel pattern and between the gate electrode and the capping layer.

40. The semiconductor device of claim 38, wherein the capping layer comprises silicon nitride.

41. A method of forming a gate structure, comprising:

forming a gate insulation layer on a substrate, the gate insulation layer including inner and outer surfaces; and

forming a gate electrode making contact with the inner surface of the gate insulation layer.

42. The method of claim 41, prior to forming a gate insulation layer, further comprising:

forming a sacrificial layer on the substrate;

forming a first opening on the sacrificial layer by partially etching the sacrificial layer, so that the substrate is partially exposed through the first opening; and

forming a single-crystalline silicon layer along an inner surface of the first opening, thereby forming a single-crystalline silicon pattern in accordance with a shape of the first opening, wherein an outer side surface of the gate insulation layer makes contact with upper and inner surfaces of the single-crystalline silicon pattern, and an inner side surface of the gate insulation layer encloses a space defined by the first opening.

43. The method of claim 42, further comprising forming a capping layer on the sacrificial layer, the capping layer having a second opening that partially exposes a surface of the sacrificial layer, wherein the sacrificial layer is etched away using the capping layer as an etching mask.

44. The method of claim 43, wherein the sacrificial layer is etched so that a bottom surface of the first opening is lower than a surface of the substrate.

45. The method of claim 44, wherein forming the gate electrode includes:

forming a conductive layer filling up the first and second openings; and

etching an upper portion of the conductive layer, so that the surface of the sacrificial layer is exposed.

46. The method of claim 42, wherein forming the sacrificial layer comprises forming a silicon germanium layer by an epitaxial process.

47. The method of claim 42, wherein the single-crystalline silicon layer is formed by an epitaxial process.

48. The method of claim 41, wherein the gate insulation layer includes at least one selected form the group consisting of a silicon oxide (SixOy, wherein x and y are positive numbers) layer, a silicon oxynitride (SiON) layer, a tantalum oxide (Ta₂O₅) layer, a tantalum oxynitride (TaON) layer, a titanium oxide (TiO₂) layer, an aluminum oxide (Al₂O₃) layer, a yttrium oxide (Y₂O₃) layer, a zirconium oxide (ZrO₂) layer, a hafnium oxide (HfO₂) layer, a barium titanate oxide (BaTiO₃) layer, a strontium titanate oxide (SrTiO₃) layer, and combinations thereof.

49. The method of claim 41, wherein the gate insulation layer is formed to a thickness of about 10 Å

to about 70 Å

.

50. The method of claim 41, wherein forming the gate electrode comprises forming a polysilicon layer doped with impurities.

51. The method of claim 50, further comprising forming a metal silicide layer on a top surface of the polysilicon layer.

52. The method of claim 51, wherein the metal silicide layer comprises at least one selected from the group consisting of tungsten silicide, titanium silicide, tantalum silicide, cobalt silicide, and nickel silicide.

53. The method of claim 41, wherein forming the gate electrode includes:

forming a polysilicon pattern into a cylindrical shape on an inner side surface of the gate insulation layer, the polysilicon pattern being doped with impurities; and

forming a metal silicide plug filling an inside of the cylindrical shaped polysilicon pattern.

54. The method of claim 41, wherein the gate electrode comprises at least one selected from the group consisting of tungsten, titanium, tantalum, cobalt, nickel, molybdenum, and ruthenium.

55. A method of manufacturing a semiconductor device, comprising:

forming a first conductive pattern on a substrate;

forming a second conductive pattern spaced apart from the first conductive pattern by a predetermined distance in a vertical direction;

forming a channel pattern including inner and outer side surfaces, the channel pattern making contact with the first and second patterns;

forming a gate insulation layer on the inner side surface of the channel pattern; and

forming a gate electrode making contact with the gate insulation layer.

56. The method of claim 55, wherein the first and second conductive patterns are partially overlapped with each other.

57. The method of claim 55, wherein the channel pattern has a pillar ring shape extending from the substrate in the vertical direction.

58. The method of claim 55, wherein the channel pattern is formed by the first and second conductive patterns.

59. The method of claim 55, wherein the first and second conductive patterns extend in horizontal direction different from each other.

60. The method of claim 55, wherein the first and second conductive patterns horizontally extend in a same direction, and the first conductive pattern extends longer than the second conductive pattern.

61. The method of claim 55, wherein forming the first conductive pattern includes:

forming a single-crystalline silicon layer on the substrate by an epitaxial process;

doping the single-crystalline silicon layer with first impurities, so that the single-crystalline silicon layer is transformed into a first conductive layer; and

patterning the first conductive layer.

62. The method of claim 61, further comprising forming a buffer oxide layer on the single-crystalline silicon layer.

63. The method of claim 62, wherein doping the single-crystalline silicon layer is carried out by an ion implantation process.

64. The method of claim 61, wherein the single-crystalline silicon is formed to a thickness of about 400 Å

to about 600 Å

.

65. The method of claim 61, before the first conductive pattern is formed, further comprising doping a surface portion of the substrate with second impurities having a conductive type different from that of the first impurities.

66. The method of claim 55, wherein forming the first conductive pattern includes:

forming a silicon germanium layer on the substrate by an epitaxial process;

forming a single-crystalline silicon layer on the silicon germanium layer by an epitaxial process;

doping the single-crystalline silicon layer with first impurities, so that the single-crystalline silicon layer is transformed into a first conductive layer; and

patterning the first conductive layer.

67. The method of claim 66, before the first conductive pattern is formed, further comprising doping a surface portion of the substrate with second impurities having a conductive type different from that of the first impurities.

68. The method of claim 55, further comprising forming a sacrificial layer on the substrate on which the first conductive pattern is formed.

69. The method of claim 68, wherein the sacrificial layer includes a silicon germanium layer formed by an epitaxial process.

70. The method of claim 68, further comprising planarizing the sacrificial layer.

71. The method of claim 68, wherein forming the sacrificial layer includes:

forming a first dummy layer on the substrate on which the first conductive pattern is formed;

planarizing the first dummy layer; and

forming a second dummy layer on the first dummy layer.

72. The method of claim 71, wherein the first dummy layer is planarized by a chemical mechanical polishing (CMP) process.

73. The method of claim 71, wherein the first dummy layer is planarized until the first conductive pattern is exposed.

74. The method of claim 71, wherein the second dummy layer is formed to a thickness of about 1000 Å

.

75. The method of claim 68, wherein forming the second conductive pattern includes:

forming a single-crystalline silicon layer on the sacrificial layer by an epitaxial process;

doping the single-crystalline silicon layer with impurities, so that the single-crystalline silicon layer is transformed into a second conductive layer;

patterning the second conductive layer;

76. The method of claim 75, wherein the single-crystalline silicon layer is formed to a thickness of about 400 Å

to about 600 Å

.

77. The method of claim 75, further comprising forming a buffer oxide layer on the single-crystalline silicon layer.

78. The method of claim 68, further comprising forming a capping layer on the sacrificial layer and the second conductive layer.

79. The method of claim 78, wherein the capping layer comprises silicon nitride.

80. The method of claim 78, further comprising planarizing the capping layer.

81. The method of claim 78, further comprising forming an opening by partially and sequentially removing the capping layer, the second conductive pattern, the sacrificial layer, and the first conductive pattern, wherein the channel pattern is formed on an inner side surface of the opening.

82. The method of claim 81, wherein the channel pattern is formed on the inner side surface of the opening by a selective epitaxial process, the opening being defined by the second conductive pattern, the sacrificial layer and the first conductive pattern.

83. The method of claim 55, wherein the channel pattern comprises single-crystalline silicon.

84. The method of claim 55, wherein the channel pattern is doped with impurities by an in-situ process during the selective epitaxial process.

85. The method of claim 81, wherein forming the gate electrode includes:

forming a third conductive layer to a thickness so that the opening is covered with the third conductive layer; and

partially removing the third conductive layer until a top surface of the capping layer is exposed.

86. The method of claim 85, wherein the third conductive layer is removed using a chemical mechanical polishing (CMP) process.

87. The method of claim 85, further comprising:

forming a hard mask on the capping layer correspondently to the second conductive pattern;

partially removing the capping layer using the hard mask to thereby form a capping pattern corresponding to the second conductive pattern;

removing the sacrificial layer from the substrate;

removing the hard mask; and

filling a space formed by removing the capping layer and the sacrificial layer with an insulation interlayer.

88. The method of claim 87, wherein the sacrificial layer is removed by a wet-etching process using an etchant in which an etching selectivity of the sacrificial layer with respect to the channel pattern is no less than about 50:

1.

89. The method of claim 81, wherein the opening is formed so that a bottom surface of the opening is lower than a surface of the substrate.

90. The method of claim 55, wherein the channel pattern is formed to a thickness of about 100 Å

to about 300 Å

.

91. The method of claim 55, wherein the gate insulation layer includes at least one selected from the group consisting of a silicon oxide (SixOy, wherein x and y are positive numbers) layer, a silicon oxynitride (SiON) layer, a tantalum oxide (Ta₂O₅) layer, a tantalum oxynitride (TaON) layer, a titanium oxide (TiO₂) layer, an aluminum oxide (Al₂O₃) layer, a yttrium oxide (Y₂O₃3) layer, a zirconium oxide (ZrO₂) layer, a hafnium oxide (HfO₂)layer, a barium titanate oxide (BaTiO₃) layer, a strontium titanate oxide (SrTiO₃) layer, and combinations thereof.

92. The method of claim 55, wherein the gate electrode comprises polysilicon doped with impurities.

93. The method of claim 55, further comprising forming a metal silicide layer on a top surface of the gate electrode.

94. The method of claim 55, wherein forming the gate electrode includes:

forming a polysilicon pattern doped with impurities into a cylindrical shape on an inner side surface of the gate insulation layer; and

forming a metal silicide plug that fills up an inside of the cylindrical shaped polysilicon pattern.

95. The method of claim 55, wherein the gate electrode comprises at least one selected from the group consisting of tungsten, titanium, tantalum, cobalt, nickel, molybdenum, and ruthenium.

96. A method of manufacturing a semiconductor device, comprising:

forming a first conductive layer on a substrate;

patterning the first conductive layer to thereby form a first conductive pattern;

forming a sacrificial layer on the substrate and the first conductive pattern;

forming a second conductive layer on the sacrificial layer;

forming a channel pattern having a pillar ring shape, the channel pattern penetrating the second conductive layer and the sacrificial layer and making contact with the first conductive pattern;

forming a gate insulation layer on an inner side surface of the pillar ring shaped channel pattern;

forming a gate electrode making contact with the gate insulation layer; and

patterning the second conductive layer to form a second conductive pattern making contact with the channel pattern.

97. The method of claim 96, wherein the first and second conductive patterns cover lower and upper portions of the channel pattern, respectively.

98. The method of claim 96, further comprising a capping layer on the second conductive layer.

99. The method of claim 98, wherein forming the channel pattern includes:

forming an opening penetrating the second conductive layer, the sacrificial layer and the first conductive pattern from a top surface of the capping layer; and

forming a single-crystalline silicon layer on an inner side surface of the opening by an epitaxial process.

100. The method of claim 99, wherein forming the gate electrode includes:

forming a third conductive layer to a thickness so that the opening is covered with the third conductive layer ; and

partially removing the third conductive layer until a top surface of the capping layer is exposed.

101. The method of claim 98, wherein patterning the second conductive layer includes:

forming a hard mask on the capping layer correspondently to the second conductive pattern; and

partially removing the capping layer and the second conductive layer using the hard mask to thereby form a second conductive pattern.

102. The method of claim 101, further comprising:

removing the sacrificial layer using an etchant in which an etching selectivity of the sacrificial layer with respect to the channel pattern is no less than about 50;

1;

filling a space with an insulation interlayer, the space being formed by removing the sacrificial layer and by partially removing the capping layer and the second conductive layer during the step of patterning the second conductive layer; and

removing the hard mask.

103. The method of claim 101, further comprising:

removing the sacrificial layer using an etchant in which an etching selectivity of the sacrificial layer with respect to the channel pattern is no less than about 50;

1;

removing the hard mask and the capping layer remaining on the second conductive pattern; and

filling a space with an insulation interlayer, the space being formed by removing the sacrificial layer, by partially removing the second conductive layer during the step of patterning the second conductive layer, and by removing the capping layer remaining on the second conductive pattern.

104. The method of claim 96, wherein the first and second conductive layers are formed by an epitaxial process, the epitaxial process being performed using a processing gas including silicon source gas and a dopant source.