System in package

• US 20050184376A1
• Filed: 02/19/2004
• Published: 08/25/2005
• Est. Priority Date: 02/19/2004
• Status: Abandoned Application

• Current Assignee: Salmon Technologies LLC
• Original Assignee: Salmon Technologies LLC
• Inventors: Salmon, Peter C.
• Application Number:
  US10/783,163
• Publication Number:
  US 20050184376A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/4867 Applying pastes or inks, e.g. screen printing H01L21/486 takes precedence
• CPC Class Codes: H01L 21/67092 Apparatus for mechanical treatment or grinding or cutting, see the relevant groups in subclasses B24B or B28D
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6638 Differential pair signal lines
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/814 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/19032 : being a microstrip line type
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H05K 1/056 : the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence

Abstract

A system in package (SIP) is fabricated on a sheet of copper foil. An interconnection circuit is fabricated on the foil using copper conductors and a dual damascene structure for each conductive layer. The preferred dielectric material is an amorphous fluorinated polymer called Cytop. Input/output traces of the interconnection circuit terminate in wells filled with solder. Chips are bumped and direct attached by inserting the bumps into the wells. The preferred bumps are gold stud bumps, and the preferred wells contain solder paste to a depth of approximately 15 microns. Imprinting is the preferred method for patterning; it enables 6-micron wide traces, 6-micron diameter vias, and a cost per well of around 0.02 cents. Stripline structures are described for a 4-layer stackup that can support operating frequencies of at least 10 GHz. New methods are proposed for testing the completed assembly and for rework of any chips that prove defective. After the assembly is fully tested and reworked in sheet form the copper foil is folded to form a stacked die package or system in package. 5-high and 9-high stacks are illustrated. The copper foil provides a low impedance thermal path for cooling every chip in the SIP.

Claims

1. A circuit board for a stacked package comprising:

an electrically conductive substrate having a plurality of foldable tabs or delineated surfaces; and

,

a multi-layer interconnection circuit having conductive traces fabricated on one or both sides of said substrate, and one or more attachment sites on one or more of said tabs or delineated surfaces, said attachment sites having terminals for connection to selected traces in said interconnection circuit.

3. The circuit board of claims 1 or 2 wherein said conductive substrate is copper or an alloy of copper.

4. The circuit board of claim 1 wherein each of said attachment terminals is either a conductive bump or a well filled with solder.

6. The circuit board of claims 1 or 2 wherein the minimum pitch of said attachment terminals is 100 microns or less.

7. The circuit board of claims 1 or 2 wherein said multi-layer interconnection circuit comprises interconnecting layers of copper conductors embedded in dielectric material.

8. The circuit board of claim 7 wherein said dielectric material includes Cytop.

9. The circuit board of claims 1 or 2 comprising:

an electrically conductive substrate which is copper or an alloy of copper;

a first dielectric layer;

a first patterned conductive layer including conductive power and signal traces;

a second dielectric layer;

a second patterned conductive layer including conductive power and signal traces;

a third dielectric layer;

a third patterned conductive layer in the form of a ground plane with feed-throughs for signals and power; and

,

a fourth dielectric layer with terminals for attachment to selected traces formed therein.

10. The circuit board of claim 9 wherein some or all of said dielectric layers are Cytop.

11. The circuit board of claim 7 wherein selected ones of said copper conductors are arranged in said dielectric material to form transmission lines having controlled impedance.

12. The circuit board of claim 7 wherein selected ones of said copper conductors are shaped and arranged in said dielectric material to form RF circuits.

2. A circuit board comprising:

an electrically conductive substrate;

a multi-layer interconnection circuit having conductive traces fabricated on one or both sides of said substrate, and one or more attachment sites which include a plurality of attachment terminals with each of said terminals adapted to connect with selected traces of said interconnection circuit, wherein each of said terminals is either a bump or a well filled with solder.

5. The circuit board of claims 2 or 4 wherein said solder is indium-based.

13. A high density cable comprising:

an electrically conductive substrate;

a multi-layer interconnection circuit having conductive traces fabricated on said substrate and at least two attachment sites wherein each of said attachment sites includes a plurality of attachment terminals and each of said terminals connects with a selected trace of said interconnection circuit.

14. The cable of claim 13 wherein said attachment terminals are either gold stud bumps or wells filled with solder.

15. The cable of claim 13 wherein said multi-layer interconnection circuit comprises interconnecting layers of copper conductors embedded in dielectric material.

16. The cable of claim 15 wherein selected ones of said copper conductors are arranged in said dielectric material to form transmission lines having a characteristic impedance.

17. The cable of claim 13 wherein the pitch of said attachment terminals is 100 microns or less.

18. The cable of claims 13-17 and including multiple branches of said cable, wherein at least one of said attachment sites is provided in each of said branches.

19. A stacked microelectronic assembly comprising:

an electrically conductive substrate having a plurality of foldable tabs or delineated surfaces;

a multi-layer interconnection circuit having conductive traces fabricated on one or both sides of said conductive substrate and one or more attachment sites on one or more of said tabs or delineated surfaces, said attachment sites having terminals for connection to selected traces in said interconnection circuit;

a plurality of microelectronic elements attached at said attachment sites using said attachment terminals; and

,

wherein at least one of said foldable tabs or delineated surfaces is folded to form a stacked arrangement of said folded tabs or delineated surfaces.

20. The stacked assembly of claim 19 wherein said electrically conductive substrate is copper or an alloy of copper.

21. The stacked assembly of claim 19 wherein each of said attachment terminals includes either a bump or a well.

22. The stacked assembly of claim 21 wherein said bump is a gold stud bump.

23. The stacked assembly of claim 21 wherein said well is filled with solder.

24. The stacked assembly of claim 23 wherein said solder is indium-based.

25. The stacked assembly of claim 19 wherein said plurality of microelectronic elements includes at least one integrated circuit chip.

26. The stacked assembly of claim 19 wherein said plurality of microelectronic elements includes at least one chip containing integrated passive devices.

27. The stacked assembly of claim 19 wherein said plurality of microelectronic elements includes at least one chip for regulating or distributing power.

28. The stacked assembly of claim 19 wherein said plurality of microelectronic elements includes at least one test chip.

29. The stacked assembly of claim 19 wherein said multi-layer interconnection circuit comprises interconnection layers of metal conductors embedded in dielectric material.

30. The stacked assembly of claim 29 wherein selected ones of said metal conductors are shaped to form RF circuits in or on said dielectric material.

31. The stacked assembly of claim 19 wherein each of said delineated surfaces is dedicated to microelectronic elements of a single type:

digital, analog, or radio frequency.

32. The stacked assembly of claim 19 wherein at least one of said attachment sites is used for attaching a cable.

33. The stacked assembly of claim 19 wherein each of said microelectronic elements is replaceable, prior to folding of said tabs.

34. A method for fabricating a stacked microelectronic assembly comprising the steps of:

a) providing an electrically conductive substrate;

b) providing a plurality of delineated surfaces-in the plane of said conductive substrate;

c) fabricating a multi-layer interconnection circuit having conductive traces on said delineated surfaces;

d) providing one or more attachment sites on at least one of said delineated surfaces, each of said attachment sites including a plurality of attachment terminals, wherein each of said terminals may connect with a selected trace of said interconnection circuit;

e) attaching a plurality of microelectronic elements at said attachment sites using said attachment terminals;

f) providing a means to test said microelectronic elements by using a test chip at-one of said attachment sites, or by using a cable connecting between one of said attachment sites and an external tester;

g) testing said microelectronic assembly using said test means and replacing any of said microelectronic elements that prove defective;

h) dicing said conductive substrate to separate said microelectronic assemblies if more than one of said assemblies is provided on said conductive substrate; and

,

i) folding one or more of said delineated surfaces to form a stack of said delineated surfaces, for each of said microelectronic assemblies.

35. A rugged microelectronic assembly comprising:

a base substrate of copper;

an interconnection circuit fabricated on said base substrate;

one or more microelectronic assemblies attached to said interconnection circuit; and

,

a top member of copper that is machined to accommodate any height variation in said assemblies.