Low leakage and data retention circuitry

• US 20050184758A1
• Filed: 01/20/2005
• Published: 08/25/2005
• Est. Priority Date: 02/19/2004
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Virtual Silicon Technology, Inc. (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Cole, Andrew, Callahan, John M., Walker, William G., Zampaglione, Michael A., Hoberman, Barry A., Hillman, Daniel L.
• Granted Patent: US 7,227,383 B2
• Time in Patent Office: Days
• US Class Current: 326/83
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/356086 with additional means for controlling the main nodes H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Claims

1. An integrated circuit comprising:

first circuitry configured to receive input signals, process the input signals, and retain data in a sleep state that has low leakage;

sleep transistor circuitry coupled to the first circuitry and configured to receive a sleep signal that has a negative voltage and reduce power consumption of the first circuitry in the state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

2. The integrated circuit of claim 1 wherein the sleep signal indicates a power up state and the sleep transistor circuitry is configured to power up the first circuitry based on the sleep signal.

3. The integrated circuit of claim 1 wherein the first circuitry is configured to receive a hold signal and retain the data based on the hold signal.

4. The integrated circuit of claim 1 wherein the first circuitry comprises master latch circuitry and slave latch circuitry and wherein the slave latch circuitry is configured to retain the data in the sleep state.

5. The integrated circuit of claim 4 wherein the slave latch circuitry comprises a medium impedance transistors configured to bias sources in the slave latch circuitry.

6. The integrated circuit of claim 4 wherein the slave latch circuitry comprises stacked transistors configured to minimize leakage.

7. The integrated circuit of claim 4 wherein the slave latch circuitry comprises multiple threshold transistors configured to minimize leakage.

8. The integrated circuit of claim 1 further comprising a power island manager configured to generate and transmit the sleep signal.

9. The integrated circuit of claim 1 wherein the first circuitry is located within a power island.

10. The integrated circuit of claim 1 further comprising an adaptive leakage controller configured to determine the negative voltage of the sleep signal.

11. The integrated circuit of claim 1 wherein the first circuitry is configured to receive a control signal to deactivate the sleep state.

12. The integrated circuit of claim 1 wherein the sleep transistor comprises an NMOS transistor.

13. A method for operating an integrated circuit, the method comprising:

receiving input signals into first circuitry;

processing the input signals in the first circuitry;

retaining data in a sleep state that has low leakage in the first circuitry;

receiving a sleep signal that has a negative voltage into sleep transistor circuitry coupled to the first circuitry; and

in the sleep transistor circuitry, reducing power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

14. The method of claim 13 wherein the sleep signal indicates a power up state and the method further comprising in the sleep transistor circuitry, powering up the first circuitry based on the sleep signal.

15. The method of claim 13 further comprising:

receiving a hold signal into the first circuitry; and

retaining the data based on the hold signal.

16. The method of claim 13 wherein the first circuitry comprises master latch circuitry and slave latch circuitry and the method further comprising in the slave latch circuitry, retaining the data in the sleep state.

17. The method of claim 16 further comprising minimizing leakage using a medium impedance transistor to bias sources in the slave latch circuitry.

18. The method of claim 16 further comprising minimizing leakage using stacked transistors in the slave latch circuitry.

19. The method of claim 16 further comprising minimizing leakage using multiple threshold transistors in the slave latch circuitry.

20. The method of claim 13 further comprising generating and transmitting the sleep signal from a power island manager.

21. The method of claim 13 wherein the first circuitry is located within a power island.

22. The method of claim 13 further comprising determining the negative voltage of the sleep signal in an adaptive leakage controller.

23. The method of claim 13 further comprising receiving a control signal to deactivate the sleep state in the first circuitry.

24. The method of claim 13 wherein the sleep transistor comprises an NMOS transistor.

25. A latching level shifter circuitry comprising:

level shifter circuitry with inputs and outputs; and

output latching circuitry comprising at least two transistors coupled to the outputs of the level shifter circuitry and configured to retain a state of the level shifter circuitry based on the inputs.