Current-controlled CMOS logic family

• US 20050184765A1
• Filed: 04/26/2005
• Published: 08/25/2005
• Est. Priority Date: 06/28/1999
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Inventors: Hairapetian, Armond
• Granted Patent: US 7,038,516 B2
• Time in Patent Office: Days
• US Class Current: 327/100
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. A circuit, comprising:

an input that is operable to receive a serial input signal that has a first frequency;

a circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to convert the serial input signal into a deserialized signal comprising a plurality of signals such that each signal of the plurality of signals has a second frequency; and

an output that is operable to transmit each signal of the plurality of signals.

2. The circuit of claim 1, wherein:

the first frequency is higher than the second frequency.

3. The circuit of claim 1, wherein:

the first frequency is an integer multiple of the second frequency.

4. The circuit of claim 1, wherein:

the output is operable to transmit each signal of the plurality of signals to at least one additional circuit block that is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated; and

the at least one additional circuit block is operable to process each signal of the plurality of signals thereby generating a plurality of processing signals.

5. The circuit of claim 1, wherein:

the output is operable to transmit each signal of the plurality of signals to a plurality of parallel processing circuitries;

each signal of the plurality of signals is provided to one corresponding processing circuitry within the plurality of parallel processing circuitries; and

the plurality of parallel processing circuitries is operable to process each signal of the plurality of signals thereby generating a plurality of processing signals.

6. The circuit of claim 5, wherein:

each processing circuitry within the plurality of parallel processing circuitries is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated.

7. The circuit of claim 1, wherein:

the circuit block is a first circuit block;

the output is operable to transmit each signal of the plurality of signals to a second circuit block that is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated;

the second circuit block is operable to process each signal of the plurality of signals thereby generating a plurality of processing signals; and

a third circuit block, implemented using C³MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, is operable to convert the plurality of processing signals into a serial output signal.

8. The circuit of claim 7, wherein:

each processed signal of the plurality of processing signals has the second frequency.

9. The circuit of claim 7, wherein:

the serial output signal has the first frequency.

10. A circuit, comprising:

an input that is operable to receive a plurality of parallel input signals such that each signal of the plurality of parallel input signals has a first frequency;

a circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to convert the plurality of parallel input signals into a serial output signal that has a second frequency; and

an output that is operable to transmit the serial output signal.

11. The circuit of claim 10, wherein:

the first frequency is lower than the second frequency.

12. The circuit of claim 10, wherein:

the second frequency is an integer multiple of the first frequency.

13. The circuit of claim 10, wherein:

the input is operable to receive each signal of the plurality of parallel input signals from at least one additional circuit block that is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated; and

the at least one additional circuit block is operable to generate the plurality of parallel input signals from at least one additional plurality of parallel input signals.

14. The circuit of claim 10, wherein:

the input is operable to receive each signal of the plurality of parallel input signals from a plurality of parallel processing circuitries;

each signal of the plurality of parallel input signals is provided from one corresponding processing circuitry within the plurality of parallel processing circuitries; and

the plurality of parallel processing circuitries is operable to generate the plurality of parallel input signals from at least one additional plurality of parallel input signals.

15. The circuit of claim 14, wherein:

each processing circuitry within the plurality of parallel processing circuitries is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated.

16. The circuit of claim 10, wherein:

the circuit block is a first circuit block;

the input is operable to receive each signal of the plurality of parallel input signals from a second circuit block that is implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated;

the second circuit block is operable to generate the plurality of parallel input signals from at least one additional plurality of parallel input signals; and

a third circuit block, implemented using C³MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, is operable to;

receive a serial input signal that has the second frequency;

convert the serial input signal into the at least one additional plurality of parallel input signals such that each signal of the at least one additional plurality of parallel input signals has the first frequency.

17. A circuit, comprising:

a first circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to;

receive a serial input signal that has a first frequency;

convert the serial input signal into a deserialized signal comprising a plurality of signals such that each signal of the plurality of signals has a second frequency; and

transmit each signal of the plurality of signals;

a second circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to;

receive each signal of the plurality of signals;

process each signal of the plurality of signals thereby generating a plurality to processed signals; and

output each processed signal of the plurality to processed signals;

a third circuit block, implemented using C³MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to;

receive each processed signal of the plurality to processed signals;

convert the plurality to processed signals into a serial output signal that has the first frequency; and

transmit the serial output signal.

18. The circuit of claim 17, wherein:

the first frequency is higher than the second frequency.

19. The circuit of claim 17, wherein:

the first frequency is an integer multiple of the second frequency.

20. The circuit of claim 17, wherein:

each processed signal of the plurality to processed signals has the second frequency.