Generation and detection of non-binary digital sequences

• US 20050184888A1
• Filed: 02/25/2005
• Published: 08/25/2005
• Est. Priority Date: 02/25/2004
• Status: Active Grant

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Granted Patent: US 7,580,472 B2
• Time in Patent Office: Days
• US Class Current: 341/57
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04J 13/10 Code generation

Abstract

Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection.

Claims

1. Apparatus for generating sequences of ternary signals that can assume one of three states, comprising:

a first sequence generator that can generate a first sequence of ternary signals that can assume one of 3 states on an output of the first sequence generator;

a second sequence generator that can generate a second sequence of ternary signals that can assume one of 3 states on an output of the second sequence generator; and

a first ternary logic device having a first input connected to the output of the first sequence generator, having a second input connected to the output of the second sequence generator and having an output;

whereby a ternary sequence appears on the output of the first ternary logic device.

2. The apparatus as claimed in claim 1, wherein the ternary logic device has an output and a third sequence of ternary signals appears on the output of the ternary logic device when the first sequence generator outputs the first sequence of ternary signals and when the second sequence generator outputs the second sequence of ternary signals.

3. The apparatus as claimed in claim 1, wherein the ternary logic device executes a ternary logic function defined by a truth table where each of its columns is a ternary reversible inverter, but not a modulo-3 adder.

4. The apparatus as claimed in claim 1 wherein the first sequence generator includes a first multi-element shift register and at least one ternary reversible logic device or function, not being the modulo-3 adder and has no multipliers.

6. The apparatus as claimed in claim 4, wherein the second sequence generator includes a second multi-element shift register.

5. The apparatus as claimed in 1 wherein the first sequence generator generates a ternary sequence, which can be characterized by:

a polynomial of degree p (with p being 2 or greater) and k (with k not greater than p-1) coefficients not equal to 0;

the length of the sequence being 3^P-1 ternary elements;

the auto-correlation, being the correlations over 2*3^P-1 positions between the sequence and its phase shifted versions shows one large absolute peak value at the coinciding phase of the sequence and its phase shifted version and is lower at all other positions.

7. Apparatus for generating a set of sequences of ternary signals that can assume one of three states, comprising:

a first sequence generator that can generate a first sequence of ternary signals that can assume one of 3 states on an output of the first sequence generator;

a second sequence generator that can generate a set of 3^P-1 different but related second sequences of ternary signals that can assume one of 3 states on an output of the second sequence generator wherein each different sequence is formed by phase shifting each element of the previous sequence by one position in a circular fashion;

a first ternary logic device having a first input connected to the output of the first sequence generator and a second input connected to the output of the second sequence generator;

wherein a set of 3^P-1 different ternary Gold sequences is generated on an output of the first ternary logic device, the set of ternary Gold sequences characterized by;

an auto-correlation with a single peak value on the coinciding phase of the correlation between the generated ternary sequence and a phase shifted copy of itself and a correlation value that is limited to a lower maximum and minimum value in all other phases; and

a cross-correlation value between each of the generated sequences that is limited to a maximum and minimum value that is lower than the peak value of the auto-correlation of each individual sequence.

8. A method for generating sequences of multi-valued signals that can assume one of x states, x being greater than or equal to three, comprising:

generating a first sequence of multi-valued signals that can assume one of x states;

generating a second sequence of multi-valued signals that can assume one of x states; and

inputting the first sequence of multi-valued signals and the second sequence of multi-valued signals to a first multi-valued logic device, the device not being a modulo-x adder.

9. The method as claimed in claim 8, further comprising outputting a third sequence of multi-valued signals on the output of the multi-valued logic device.

10. The method as claimed in claim 8, wherein the step of generating a first sequence of multi-valued signals is performed using a first multi-element shift register.

11. The method as claimed in claim 10, wherein the step of generating a second sequence of multi-valued signals is performed using a second multi-element shift register.

12. The method as claimed in claim 9, wherein the step of generating a first sequence of multi-valued signals is performed using a first multi-element shift register and at least a second multi-valued logic device that implements a second multi-valued logic function.

13. The method as claimed in claim 12, wherein the step of generating a second sequence of multi-valued signals is performed using a second multi-element shift register and at least a third multi-valued logic device that implements a third multi-valued logic function.

14. The method as claimed in claim 13, wherein the third sequence of multi-valued signals is a Gold sequence.

15. Apparatus for generating sequences of multi-value signals that can assume one of x states, x being greater than or equal to three, comprising:

a first sequence generator that can generate a first sequence of multi-value signals that can assume one of x states on an output of the first sequence generator;

a second sequence generator that can generate a second sequence of multi-value signals that can assume one of x states on an output of the second sequence generator; and

a first multi-value logic device having a first input connected to the output of the first sequence generator and having a second input connected to the output of the second sequence generator.

16. The apparatus as claimed in claim 15, wherein the multi-value logic device has an output and a third sequence of multi-value signals appears on the output of the multi-value logic device when the first sequence generator outputs the first sequence of multi-value signals and when the second sequence generator outputs the second sequence of multi-value signals.

17. The apparatus as claimed in claim 15, wherein the first sequence generator includes a first multi-element shift register.

18. The apparatus as claimed in claim 17, wherein the second sequence generator includes a second multi-element shift register.

19. The apparatus as claimed in claim 16, wherein the first sequence generator includes a first multi-element shift register and at least a second multi-value logic device that implements a second multi-value logic function.

20. The apparatus as claimed in claim 19, wherein the second sequence generator includes a second multi-element shift register and at least a third multi-value logic device that implements a third multi-value logic function.

21. The apparatus as claimed in claim 20, wherein the third sequence of multi-value signals is a Gold sequence.

22. A method for generating sequences of multi-value signals that can assume one of x states, x being greater than or equal to three, comprising:

generating a first sequence of multi-value signals that can assume one of x states;

generating a second sequence of multi-value signals that can assume one of x states; and

inputting the first sequence of multi-value signals and the second sequence of multi-value signals to a first multi-value logic device.

23. The method as claimed in claim 22, further comprising outputting a third sequence of multi-value signals on the output of the multi-value logic device.

24. The method as claimed in claim 22, wherein the step of generating a first sequence of multi-value signals is performed using a first multi-element shift register.

25. The method as claimed in claim 24, wherein the step of generating a second sequence of multi-value signals is performed using a second multi-element shift register.

26. The method as claimed in claim 23, wherein the step of generating a first sequence of multi-value signals is performed using a first multi-element shift register and at least a second multi-value logic device that implements a second multi-value logic function.

27. The method as claimed in claim 26, wherein the step of generating a second sequence of multi-value signals is performed using a second multi-element shift register and at least a third multi-value logic device that implements a third multi-value logic function.

28. The method as claimed in claim 27, wherein the third sequence of multi-value signals is a Gold sequence.