Multiprocessor computer system

• US 20050184994A1
• Filed: 03/24/2005
• Published: 08/25/2005
• Est. Priority Date: 02/11/2000
• Status: Abandoned Application

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yutaka, Teiji, Okada, Toyoshi, Tanaka, Masayoshi, Oka, Masaaki, Ohba, Akio, Suzuoki, Masakazu, Hiroi, Toshiyuki
• Application Number:
  US11/089,177
• Publication Number:
  US 20050184994A1
• Time in Patent Office: Days
• US Class Current: 345/502
• CPC Class Codes: A63F 2300/203 Image generating hardware
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

The present invention relates to the architecture and use of a computer processor optimized for instruction and data processing. The computer processor includes a main processor element in operative communication with a main memory for storing data, and sub-processor elements in operative communication with the main processor element for processing the data. Each of the sub-processor elements including a dedicated local memory for storing instructions and data. The main processor desirably comprises a primary processor core, and the sub-processor elements desirably include a set of coprocessors. One of the coprocessors may be an embedded coprocessor that performs error checking in the primary processor core. Another one of the coprocessors may be a vector processing unit. A program can directly control the vector processing unit or may indirectly control it via the primary processor core.

Claims

1. A computer processor comprising:

a main processor element in operative communication with a main memory for storing data; and

a plurality of sub-processor elements in operative communication with the main processor element for processing the data, each of the sub-processor elements including a dedicated local memory for storing instructions and data.

2. The computer processor of claim 1, wherein the dedicated local memory includes a built-in instruction memory and a data memory.

3. The computer processor of claim 1, wherein each of the sub-processor elements operates as an independent processor based on instructions stored in the dedicated local memory.

4. The computer processor of claim 3, wherein each of the sub-processor elements operates in a single instruction multiple data mode.

5. The processor of claim 1, wherein the plurality of sub-processor elements includes a pair of vector processing units and an image processing unit interconnected by an internal processor bus.

6. The processor of claim 1, wherein the main processor element comprises a primary processor core.

7. The processor of claim 6, wherein the primary processor core has a two-way super scalar architecture enabling execution of two instructions per cycle.

8. The processor of claim 6, wherein the primary processor core includes a program counter with a branch target address cache operable to perform branch predictions.

9. The processor of claim 8, wherein the primary processor core further includes:

a translation look-aside buffer for associating physical memory addresses with virtual addresses; and

an on-chip instruction cache operatively associated with the translation look-aside buffer.

10. The processor of claim 6, wherein the primary processor core includes a scratchpad memory functioning as a double buffer to hide latency of the main memory from the primary processor core.

11. The processor of claim 6, wherein the plurality of sub-processor elements includes a set of coprocessors, a first one of the coprocessors being an embedded coprocessor for error checking in the primary processor core, and a second one of the coprocessors being a vector processing unit.

12. The processor of claim 11, wherein a program indirectly controls the vector processing unit through the primary processor core in a first mode and directly controls the vector processing unit in a second mode.

13. The processor of claim 12, wherein the first mode has a first instruction set associated therewith and the second mode has a second instruction set associated therewith, the second instruction set being different from the first instruction set.

14. The processor of claim 12, wherein operation resources and registers of the vector processing unit are operated directly by the primary processor core in the first mode.

15. The processor of claim 12, wherein the vector processing unit is operable to execute programs independently from the primary processor core in the second mode.

16. The processor of claim 15, wherein the dedicated local memory of the vector processing unit includes an instruction memory, and the vector processing unit executes programs in the second mode by implementing instructions stored in the instruction memory.

17. The processor claim 11, wherein the vector processing unit comprises means for simultaneously performing a floating point product sum calculation and a floating point division or an integer calculation.

18. The processor of claim 11, wherein the processor further includes a vector interface that is operatively coupled to the vector processing unit and is operable to perform a data packing function.

19. The processor of claim 18, wherein the vector interface is operable to initiate program execution.

20. The processor of claim 11, wherein the vector processing unit includes first and second vector processing units, the first vector processing unit being operable to function in both a coprocessing mode and stand alone mode, and the second vector processing unit being operable to function only in the stand alone mode.

21. The processor of claim 20, further comprising a graphics processor interface for arbitrating between the second vector processing unit and the primary processor core and the first vector processing unit.

22. The processor of claim 11, further comprising an image processing unit operatively connected to the primary processor core and at least some of the coprocessors, the image processing unit being operable to interpret and decode an MPEG bitstream.