Device for amplitude adjustment and rectification made with MOS technology

• US 20050185433A1
• Filed: 01/04/2005
• Published: 08/25/2005
• Est. Priority Date: 06/26/1998
• Status: Active Grant

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Maejima, Toshio
• Granted Patent: US 7,215,191 B2
• Time in Patent Office: Days
• US Class Current: 363/125
• CPC Class Codes: H03G 3/3026 the gain being discontinuously variable, e.g. controlled by switching
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics. A full-wave rectifier, applicable to the amplitude adjustment device, is mainly configured by an inversion amplifier, an amplifier and an output section. Herein, the inversion amplifier amplifies an input signal with a gain of “−1”, while the amplifier amplifies it with a gain of “1”. Outputs of the amplifiers differ from each other in phases by 180°. The output section produces a full-wave rectified signal based on the outputs of the amplifiers. Incidentally, all of the amplifiers and output section are configured using field-effect transistors without using diodes being externally connected. Hence, it is possible to manufacture the full-wave rectifier in a form of an IC in accordance with the MOS process with ease.

Claims

1. A full-wave rectifier which produces a full-wave rectified signal by effecting full-wave rectification on an input signal, comprising:

an amplifier for producing a first output signal whose phase is identical to a phase of the input signal;

an inversion amplifier for producing a second output signal whose phase is reverse to the phase of the input signal; and

an output section for switching over the first output signal and the second output signal to output the full-wave rectified signal.

2. A full-wave rectifier according to claim 1 wherein each of the amplifier and inversion amplifier is configured using field-effect transistors and is of a feedback type to feed back the full-wave rectified signal thereto, and wherein the output section is equipped with a constant current source for supplying a constant current, a first field-effect transistor whose connection terminal is connected to the constant current source and whose control terminal receives the first output signal of the amplifier, and a second field-effect transistor whose connection terminal is connected to the constant current source and whose control terminal receives the second output signal of the inversion amplifier, so that the full-wave rectified signal is extracted from the connection terminals of the first and second field-effect transistors.

3. A full-wave rectifier comprising:

an inversion amplifier having a first inverting input to which an input signal is applied and to which an output signal corresponding to a full-wave rectified signal is fed back, the inversion amplifier amplifying the input signal with a gain of “

−

1”

to produce a first output signal whose level is increased relatively high only in a first half duration of one period of the input signal;

an amplifier having a second inverting input to which the output signal is fed back, the amplifier amplifying the input signal with a gain of “

1”

to produce a second output signal whose level is increased relatively high only in a second half duration of one period of the input signal; and

an output section for producing a first portion of the full-wave rectified signal based on the first output signal of the inversion amplifier in the first half duration and for producing a second portion of the full-wave rectified signal based on the second output signal of the amplifier in the second half duration, wherein the first portion and the second portion are combined together to form a negative waveform for the full-wave rectified signal in response to one period of the input signal.

4. A full-wave rectifier according to claim 3 wherein the inversion amplifier is configured using a first field-effect transistor whose gate corresponds to the first inverting input and a second field-effect transistor whose drain provides the first output signal.

5. A full-wave rectifier according to claim 4 wherein the amplifier is configured using a third field-effect transistor whose gate receives the input signal and whose drain provides the second output signal, and a fourth field-effect transistor whose gate corresponds to the second inverting input.

6. A full-wave rectifier according to claim 5 wherein the output section is configured using a pair of field-effect transistors whose drains are connected together to provide the output signal and whose gates receive the first and second output signals respectively

7. A full-wave rectifier comprising:

an amplifier having a first inverting input to which an output signal corresponding to a full-wave rectified signal is fed back, the amplifier amplifying the input signal with a gain of “

1”

to produce a first output signal whose level is reduced relatively low only in a first half duration of one period of the input signal;

an inversion amplifier having a second inverting input to which an input signal is applied and to which the output signal is fed back, the inversion amplifier amplifying the input signal with a gain of “

−

1”

to produce a second output signal whose level is reduced relatively low only in a second half duration of one period of the input signal;

an output section for producing a first portion of the full-wave rectified signal based on the first output signal of the amplifier in the first half duration and for producing a second portion of the full-wave rectified signal based on the second output signal of the inversion amplifier in the second half duration, wherein the first portion and the second portion are combined together to form a positive waveform for the full-wave rectified signal in response to one period of the input signal.

8. A full-wave rectifier according to claim 7 wherein the inversion amplifier is configured using a first d field-effect transistor whose gate corresponds to the second inverting input and a second field-effect transistor whose drain provides the second output signal.

9. A full-wave rectifier according to claim 8 wherein the amplifier is configured using a third field-effect transistor whose gate receives the input signal and whose drain provides the first output signal, and a fourth field-effect transistor whose gate corresponds to the first inverting input.

10. A full-wave rectifier according to claim 9 wherein the output section is configured using a pair of field-effect transistors whose drains are connected together to provide the output signal and whose gates receive the first and second output signals respectively.