Nonvolatile memory and data processing system

• US 20050185463A1
• Filed: 02/16/2005
• Published: 08/25/2005
• Est. Priority Date: 02/20/2004
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Fukasawa, Shinichi, Iida, Tetsuya, Kanamori, Motoki, Kurakata, Shigeo, Asari, Shinsuke
• Application Number:
  US11/058,672
• Publication Number:
  US 20050185463A1
• Time in Patent Office: Days
• US Class Current: 365/185.40
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory

Abstract

The present invention provides a nonvolatile memory which includes a card controller, a reprogrammable nonvolatile memory and an IC card chip. The card controller is capable of outputting at least one of reset response information (ATR) outputted from the IC card chip in response to a reset instruction to the IC card chip and information indicative of an erase unit of a flash memory to the outside in response to a predetermined command supplied from outside. A card host is capable of causing the card controller to change an operating speed or operating frequency or the like of the IC card chip by reference to the ATR information. Upon reprogramming of memory information with respect to the reprogrammable nonvolatile memory, the card host is capable of sending write data equivalent to an amount commensurate with an erase unit to the nonvolatile memory by reference to the information indicative of the erase unit and giving write instructions.

Claims

1. A nonvolatile memory comprising:

an interface controller;

a reprogrammable nonvolatile memory; and

a security controller which performs security processing of data,

wherein the interface controller is capable of outputting response information which is at least one of reset response information outputted by the security controller in response to a reset instruction to the security controller and information indicative of an erase unit of a storage area of the reprogrammable nonvolatile memory to the outside, in response to a first command supplied to the interface controller from outside.

2. The nonvolatile memory according to claim 1,

wherein the interface controller extracts security processing information contained in a second command supplied from outside, in response to the second command, and supplies the security processing information to the security controller, and

wherein the interface controller outputs the result of security processing by the security controller to the outside in response to a third command supplied from outside.

3. The nonvolatile memory according to claim 1, wherein the interface controller has a volatile memory circuit which latches said response information in response to a reset command of the nonvolatile memory and outputs the one information held in the volatile memory circuit to the outside of a memory card in response to the predetermined first command.

4. The nonvolatile memory according to claim 3, wherein said response information latched in the volatile memory circuit is read from the reprogrammable nonvolatile memory.

5. The nonvolatile memory according to claim 1, wherein the first command has a command code different from the reset command of the nonvolatile memory.

6. The nonvolatile memory according to claim 1,

wherein the first command corresponds to the reset command of the nonvolatile memory, and

wherein the interface controller outputs said response information to the outside following a response to reset processing.

7. The nonvolatile memory according to claim 1,

wherein the first command is a read command relative to a predetermined register held in the interface controller, and

wherein the interface controller outputs the response information to the outside together with information retained in the register.

8. The nonvolatile memory according to claim 1, wherein the reset response information of the security controller includes an operation limit frequency and historical byte information of the security controller.

9. The nonvolatile memory according to claim 1, wherein the information indicative of the erase unit of the storage area of the reprogrammable nonvolatile memory is a device code indicative of the type of reprogrammable nonvolatile memory, or number-of-data information corresponding to the erase unit, generated based on the device code.

10. The nonvolatile memory according to claim 1, wherein the interface controller is capable of changing the frequency of a clock signal supplied to the security controller in response to a frequency setting command.

11. A data processing system comprising:

a nonvolatile memory as defined in claim 1, which is mountable thereto,

wherein the first command for outputting the response information including the reset response information is outputted to the nonvolatile memory, the reset response information outputted from the nonvolatile memory is inputted in response to the first command, and the setting of an operating frequency of the security controller is changeable by reference to the inputted reset response information.

12. A data processing system comprising:

a nonvolatile memory as defined in claim 1, which is mountable thereto,

wherein the first command for outputting the response information including the information indicative of the erase unit of the storage area is outputted to the nonvolatile memory, the information indicative of the ease unit of the storage area, which is outputted from the nonvolatile memory, is inputted in response to the first command, and the number of transfers of write data to the nonvolatile memory is set for each erase unit, based on the inputted information indicative of the erase unit.

13. A nonvolatile memory comprising:

an interface controller; and

a reprogrammable nonvolatile memory,

wherein the interface controller is capable of outputting first information indicative of an erase unit of a storage area of the reprogrammable nonvolatile memory to the outside in response to a first command supplied to the interface controller from outside.

14. The nonvolatile memory according to claim 13,

wherein the first command is a reset command of the nonvolatile memory, and

wherein the interface controller performs reset processing of the nonvolatile memory itself and outputs the first information indicative of the erase unit to the outside following a response to the reset command.

15. The nonvolatile memory according to claim 13,

wherein the first command is a read command relative to a predetermined register held in the interface controller, and

wherein the interface controller outputs the first information indicative of the erase unit to the outside together with information retained in the register.

16. The nonvolatile memory according to claim 13, wherein the first information indicative of the erase unit is a device code indicative of the type of reprogrammable nonvolatile memory, or number-of-data information corresponding to an erase unit of a storage area, generated based on the device code.

17. The nonvolatile memory according to claim 13, wherein the interface controller acquires a device code indicative of the type of reprogrammable nonvolatile memory from the reprogrammable nonvolatile memory, acquires an operation limit frequency of the reprogrammable nonvolatile memory based on the acquired device code, and outputs the operation limit frequency to the outside in response to the first command.

18. The nonvolatile memory according to claim 17, wherein the interface controller is capable of changing the frequency of a clock signal supplied to the reprogrammable nonvolatile memory in response to a frequency setting command.