×

Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm

  • US 20050185464A1
  • Filed: 02/24/2004
  • Published: 08/25/2005
  • Est. Priority Date: 02/24/2004
  • Status: Active Grant
First Claim
Patent Images

1. A floating gate memory array, comprising:

  • a) an array of floating gate memory cells, b) a source line coupled to cells in a row of said array, c) a word line coupled to control gates of transistors of said memory cells in the row of said array, d) a read bit line and a program bit line connecting between said memory cells in each column of said array.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×