Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm
First Claim
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1. A floating gate memory array, comprising:
- a) an array of floating gate memory cells, b) a source line coupled to cells in a row of said array, c) a word line coupled to control gates of transistors of said memory cells in the row of said array, d) a read bit line and a program bit line connecting between said memory cells in each column of said array.
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Abstract
Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
26 Citations
41 Claims
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1. A floating gate memory array, comprising:
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a) an array of floating gate memory cells, b) a source line coupled to cells in a row of said array, c) a word line coupled to control gates of transistors of said memory cells in the row of said array, d) a read bit line and a program bit line connecting between said memory cells in each column of said array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for re-write if disturbed, comprising:
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a) loading input address and data into a page buffer, b) reading out original data from an address location of an array to a page buffer, c) erasing said address location, verifying the erasing of said address location, and erasing bytes failing verification, d) programming said address location, verifying the programming of said address location, programming bytes failing programming, e) verifying data in unchanged portion of said address location f) ending if verification of unchanged portion of said address location is passed, else re-write failed locations. - View Dependent Claims (13, 14)
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15. A memory array utilizing cells with one split gate transistor, comprising:
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a) a means for forming an array of one transistor split gate cells into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells, b) a means for connecting a split source line to said even and odd addressed cells, c) a means for connecting said first row with a first word line and said second row with a second word line, d) a means for connecting cells in a column to a bit line. - View Dependent Claims (16, 17, 18)
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19. A memory array utilizing cells with two split gate transistors, comprising:
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a) a means for forming an array of two transistor split gate cells into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells, b) a means for connecting a split source line to said even and odd addressed cells, c) a means for connecting said first row with a first word line and said second row with a second word line, d) a means for connecting cells in a column to a program bit line and a read bit line. - View Dependent Claims (20, 21, 22, 23)
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24. A memory array utilizing cells with three split gate transistors, comprising:
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a) a means for forming an array of cells containing three split gate transistors into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells, b) a means for sharing a floating gate between a first and a second split gate transistor of said three split gate transistors, c) a means for sharing a source line between said even and odd addressed cells, d) a means for connecting said first row with a first word line and said second row with a second word line, e) a means for connecting between cells in a column with a first program bit line, a second program bit line and a read bit line. - View Dependent Claims (25, 26, 27, 28)
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29. A memory array utilizing cells with two split gate transistors, comprising:
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a) a means for forming an array of cells containing two split gate transistors into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells, b) a means for sharing a floating gate between a first and a second split gate transistor of said two split gate transistors, c) a means for sharing a source line between said even and odd addressed cells, d) a means for connecting said first row with a first word line and said second row with a second word line, e) a means for connecting between cells in a column with a first program bit line, a second program bit line and a read bit line. - View Dependent Claims (30, 31, 32, 33)
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34. A memory array containing cells with two split gate transistors, comprising:
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a) a means for forming into rows and columns an array of cells containing two split gate transistors, b) a means for sharing a floating gate between a first and a second split gate transistor of said two split gate transistors, c) a means for increasing the threshold voltage of said first split gate transistor, d) a means for sharing a source line between said even and odd addressed cells, e) a means for connecting said first row with a first word line and said second row with a second word line, f) a means for connecting between cells in a column with a program bit line and a read bit line. - View Dependent Claims (35, 36, 37, 38)
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39. A method for re-writing disturbed cells, comprising:
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a) a means for loading a page buffer with input addresses and data, b) a means for reading data from a memory location into said page buffer, c) a means for erasing said address location and re-erasing those bytes failing verification of said erasing, d) a means for programming said memory location and re-programming those bytes failing verification of said programming, e) a means for verifying data in unchanged portion of said memory location and ending process if verification is true, else return to step c) to re-program data. - View Dependent Claims (40, 41)
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Specification