Method and apparatus for a parallel correlator and applications thereof
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Abstract
A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, X0 is multiplied by each state (C0(0) through C0(k-1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k-1). This is repeating for data bits (X1-XM-1) and corresponding coefficients (C1-CM-1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated. The final layer of results includes a separate correlation output for each possible state of the complete set of coefficients (C0-CM-1). The final layer of results is compared to identify a most likely code encoded on said data word. In an embodiment, the summations are pruned to exclude summations that would result in invalid combinations of the encoding coefficients (C0-CM-1). In an embodiment, substantially the same hardware is utilized for processing in-phase and quadrature phase components of the data word (X0-XM-1). In an embodiment, the coefficients (C0-CM-1) represent real numbers. In an alternative embodiment, the coefficients (C0-CM-1) represent complex numbers. In an embodiment, the coefficients (C0-CM-1) are represented with a single bit. Alternatively, the coefficients (C0-CM-1) are represented with multiple bits (e.g., magnitude). In an embodiment, the coefficients (C0-CM-1) represent a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.
102 Citations
51 Claims
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1-32. -32. (canceled)
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33. A wireless local area network (WLAN) device, comprising:
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means for generating in parallel the correlation of a data word vector (X0, . . . , XM-1) with each valid combination of a coefficient set (C0, . . . , CM-1); and
means for identifying the correlation corresponding to a code encoded on the data word. - View Dependent Claims (34, 35, 36, 37, 38)
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39. A wireless local area network (WLAN) device, comprising:
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a plurality of inputs, one for each element of an encoded data word vector (X0, . . . XM-1);
a multiplier module having a coefficient set (C0, . . . , CM-1), wherein each coefficient in the coefficient set has one or more possible states, wherein the multiplier module receives the plurality of inputs and multiplies each input with each state of a corresponding coefficient;
a first summation module including a plurality of summers, each summer coupled to a different group of multiplier module outputs, wherein each group of multiplier module outputs represents a valid combination of multiplier module outputs, and wherein a first set of correlation results are output in parallel from the first summation tier;
one or more additional summation modules coupled in series, each additional summation module receiving the outputs from a previous summation module, wherein the one or more additional summation modules includes a final summation module and wherein the final summation module outputs in parallel the correlation of the data word vector with each valid combination of the coefficient set; and
a comparator coupled to the final summation module. - View Dependent Claims (40, 41, 42, 43)
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44. A wireless local area network (WLAN) device, comprising:
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a multiplier module having a coefficient set (C0, . . . , CM-1), wherein each coefficient in the coefficient set has one or more possible states, wherein the multiplier module receives a plurality of inputs, one for each element of an encoded data word vector (X0, . . . , XM-1), and multiplies each input with each state of a corresponding coefficient;
a first summation module including a plurality of adders, wherein each adder receives a valid combination of multiplier module outputs and wherein an output of each adder in the first summation module includes two correlation components;
a second summation module including a plurality of adders, wherein each adder receives a valid combination of first summation module outputs and wherein an output of each adder in the second summation module includes four correlation components; and
a final summation module including a plurality adders, wherein each adder receives a valid combination of second summation module outputs and wherein the output of the final summation module is 64 valid correlations, each correlation having eight correlation components. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51)
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Specification