Ternary and multi-value digital signal scramblers, descramblers and sequence generators

• US 20050185796A1
• Filed: 09/08/2004
• Published: 08/25/2005
• Est. Priority Date: 02/25/2004
• Status: Active Grant

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Granted Patent: US 7,643,632 B2
• Time in Patent Office: Days
• US Class Current: 380/268
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.

Claims

1. A method of scrambling a ternary signal with a scrambler, the ternary signal being able to assume one of three states and the scrambler having a first scrambling ternary logic device that implements a ternary logic function, sc, and a scrambling logic circuit, comprising:

inputting the ternary signal and an output from the scrambling logic circuit to the first scrambling ternary logic device;

inputting an output from the first scrambling ternary logic device to the scrambling logic circuit;

wherein the ternary logic function, sc, can be specified by a scrambling ternary truth table having three columns, each of the columns being defined by a ternary inverter;

whereby the output from the first scrambling ternary logic device is a scrambled version of the ternary signal.

2. The method as claimed in claim 1, wherein each column is defined by one of the following ternary inverters i₁ to i₆, as long as each column is not defined by i₁:

i₁ i₂ i₃ i₄ i₅ i₆ 0 0 0 1 1 2 2 1 1 2 0 2 0 1 2 2 1 2 0 1 0

3. The method as claimed in claim 2, wherein at least two different ternary inverters define the scrambling ternary truth table.

4. The method as claimed in claim 2, wherein three different ternary inverters define the scrambling ternary truth table.

5. The method as claimed in claim 1, wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device.

6. The method as claimed in claim 2, wherein the scrambled version of the ternary signal is descrambled with a descrambling device having a first descrambling ternary logic device and a descrambling logic circuit, the first descrambling ternary logic device implementing a ternary logic function, dc, the method comprising:

inputting the scrambled version of the ternary signal to the first descrambling ternary logic device and to the descrambling logic circuit;

inputting an output from the descrambling logic circuit to the first descrambling ternary logic device; and

outputting a descrambled ternary signal on an output of the first descrambling ternary logic device;

wherein the ternary logic function, dc, can be specified by a descrambling ternary truth table having three columns, each of the columns being defined by one of the ternary inverters i₁ to i₆ and wherein the descrambling logic circuit is the same as the scrambling logic circuit.

7. The method as claimed in claim 6, wherein a column in the descrambling ternary truth table is defined by:

the same inverter that defines the corresponding column in the scrambling ternary truth table if the inverter is i₁, i₂, i₃ or i₆;

the inverter i₅ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₄; and

the inverter i₄ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₅.

8. The method as claimed in claim 6, wherein a column in the descrambling ternary truth table is defined by:

the same inverter that defines the corresponding column in the scrambling ternary truth table if the inverter is self reversing; and

a different inverter if the corresponding column in the scrambling ternary truth table is defined by a reversible inverter that is not self-reversing.

9. The method as claimed in claim 6 wherein:

the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device, and

the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling ternary logic device, and wherein the output from the second descrambling ternary logic device is provided to an input of the first descrambling ternary logic device and the scrambled version of the ternary signal is input to the descrambling n-length shift register.

10. Apparatus for scrambling a ternary signal that can assume one of three states, comprising:

a first scrambling ternary logic device that implements a ternary logic function, sc, the first scrambling ternary logic device having a first and second input and an output;

a scrambling logic circuit having an input and an output;

wherein the ternary signal is input to the first input of the first scrambling ternary logic device, the output of the scrambling logic circuit is input to the second input of the first scrambling ternary logic device and the output of the first scrambling ternary logic device is provided to the input of the scrambling logic circuit,

wherein the ternary logic function, sc, can be specified by a scrambling ternary truth table having three columns, each of the columns being defined by a ternary inverter;

whereby a scrambled ternary signal is provided on the output of the first scrambling ternary logic device.

11. The apparatus as claimed in claim 10, wherein each column is defined by one of the following ternary inverters i₁ to i₆, as long as each column is not defined by i₁:

i₁ i₂ i₃ i₄ i₅ i₆ 0 0 0 1 1 2 2 1 1 2 0 2 0 1 2 2 1 2 0 1 0

12. The apparatus as claimed in claim 11, wherein at least two different ternary inverters define the scrambling ternary truth table.

13. The apparatus in claim 11, wherein three different ternary inverters define the scrambling ternary truth table.

14. The apparatus as claimed in claim 10, wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device.

15. The apparatus as claimed in claim 11, further including a descrambler for descrambling the scrambled ternary signal, comprising:

a first descrambling ternary logic device that implements the ternary logic function, dc, the first descrambling ternary logic device having a first and second input and an output;

a descrambling logic circuit having an input and an output;

wherein the scrambled ternary signal is input to the first input of the first descrambling ternary logic device and to the input of the descrambling logic device and the output of the descrambling logic device is input to the second input of the first descrambling ternary logic device;

wherein the ternary logic function, dc, can be specified by a descrambling ternary truth table having three columns, each of the columns being defined by one of the ternary inverters, i₁ to i₆ and wherein the descrambling logic circuit is the same as the scrambling logic circuit;

whereby a descrambled ternary signal is provided on the output of the first descrambling ternary logic device.

16. The apparatus as claimed in claim 15, wherein a column in the descrambling ternary truth table is defined by:

the same inverter that defines the corresponding column in the scrambling ternary truth table if the inverter is i₁, i₂, i₃ or i₆;

the inverter i₅ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₄; and

the inverter i₄ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₅.

17. The apparatus as claimed in claim 15, wherein a column in the descrambling ternary truth table is defined by:

the same inverter that defines the corresponding column in the scrambling ternary truth table if the inverter is self reversing; and

a different inverter if the corresponding column in the scrambling ternary truth table is defined by a reversible inverter that is not self-reversing.

18. The apparatus as claimed in claim 15 wherein:

the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device, and

the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling ternary logic device, and wherein the output from the second descrambling ternary logic device is provided to an input of the first descrambling ternary logic device and the scrambled version of the ternary signal is input to the descrambling n-length shift register.

19. A method of scrambling a multi-value signal that can assume one of x states, wherein x is greater than or equal to 4, with a scrambler, the scrambler having a first scrambling multi-value logic device that implements a multi-value logic function, fsc, and a scrambling logic circuit, comprising:

inputting the multi-value signal and an output from the scrambling logic circuit to the first scrambling multi-value logic device;

inputting an output from the first scrambling multi-value logic device to an input to the scrambling logic circuit;

wherein the multi-value logic function, fsc, can be specified by a multi-value scrambling truth table having x columns, each of the columns being defined by a multi-value inverter;

whereby the output from the first scrambling multi-value logic device is a scrambled version of the multi-value signal.

20. The method as claimed in claim 19, wherein x equals 4 and each column is defined by one of the following multi-value inverters i₁ to i₂₄, as long as each column is not defined by i₁:

i₁ i₂ i₃ i₄ i₅ i₆ I₇ i₈ i₉ i₁₀ i₁₁ i₁₂ i₁₃ i₁₄ i₁₅ I₁₆ i₁₇ i₁₈ i₁₉ i₂₀ i₂₁ i₂₂ i₂₃ i₂₄ 0 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 1 1 1 2 2 3 3 0 0 2 2 3 3 0 0 1 1 3 3 0 0 1 1 2 2 2 2 3 1 3 1 2 2 3 0 3 0 2 1 3 0 3 0 1 1 2 0 2 0 1 3 3 2 3 1 2 1 3 2 3 0 2 0 3 1 3 0 1 0 2 1 2 0 1 0

21. The method as claimed in claim 20, wherein at least two different multi-value inverters define the multi-value truth table.

22. The method as claimed in claim 20, wherein at least three different multi-value inverters define the multi-value truth table.

23. The method as claimed in claim 20, wherein four different multi-value inverters define the multi-value truth table.

24. The method as claimed in claim 19, wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device.

25. The method as claimed in claim 20, wherein the scrambled version of the multi-value signal is descrambled with a descrambling device having a first descrambling multi-value logic device and a descrambling logic circuit, the first descrambling multi-value logic device implementing a multi-value logic function, fdc, the method comprising:

inputting the scrambled version of the multi-value signal to the first descrambling multi-value logic device and to the descrambling logic circuit;

inputting an output from the descrambling logic circuit to the first descrambling multi-value logic device; and

outputting a descrambled multi-value signal on an output of the first descrambling multi-value logic device;

wherein the multi-value logic function, fdc, can be specified by a descrambling multi-value truth table having x columns, each of the columns being defined by one of the ternary inverters i₁ to i₂₄ and wherein the descrambling logic circuit is the same as the scrambling logic circuit.

26. The method as claimed in claim 25, wherein a column in the descrambling multi-value truth table is defined by:

the same inverter that defines the corresponding column in the scrambling multi-value truth table if the inverter is self reversing; and

a different inverter if the corresponding column in the scrambling multi-value truth table is defined by a reversible inverter that is not self-reversing.

27. The method as claimed in claim 19 wherein:

the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device, and

the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling multi-value logic device, and wherein the output from the second descrambling multi-value logic device is provided to an input of the first descrambling multi-value logic device and the scrambled version of the multi-value signal is input to the descrambling n-length shift register.

28. Apparatus for scrambling a multi-value signal that can assume one of x states, wherein x is greater than or equal to 4, comprising:

a first scrambling multi-value logic device that implements a multi-value logic function, fc, the first multi-value logic device having a first and second input and an output;

a scrambling logic circuit having an input and an output;

wherein the multi-value signal is input to the first input of the first scrambling multi-value logic device, the output of the scrambling logic circuit is input to the second input of the first scrambling multi-value logic device and the output of the first scrambling multi-value logic device is input to the input of the scrambling logic circuit,

wherein the multi-value logic function, fc, can be specified by a multi-value scrambling truth table having x columns, each of the columns being defined by the application of one or more multi-value inverters to each column;

whereby a scrambled multi-value signal is provided on the output of the first scrambling multi-value logic device.

29. The apparatus as claimed in claim 28, wherein x equals 4 and each column is defined by one of the following multi-value inverters i₁ to i₂₄, as long as each column is not defined by i₁:

i₁ i₂ I₃ i₄ i₅ i₆ i₇ i₈ i₉ i₁₀ i₁₁ i₁₂ i₁₃ i₁₄ i₁₅ i₁₆ i₁₇ i₁₈ i₁₉ i₂₀ i₂₁ i₂₂ i₂₃ i₂₄ 0 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 1 1 1 2 2 3 3 0 0 2 2 3 3 0 0 1 1 3 3 0 0 1 1 2 2 2 2 3 1 3 1 2 2 3 0 3 0 2 1 3 0 3 0 1 1 2 0 2 0 1 3 3 2 3 1 2 1 3 2 3 0 2 0 3 1 3 0 1 0 2 1 2 0 1 0

30. The apparatus as claimed in claim 29, wherein at least two different multi-value inverters define the multi-value scrambling truth table.

31. The apparatus as claimed in claim 29, wherein at least different three multi-value inverters define the multi-value scrambling truth table.

32. The apparatus as claimed in claim 29, wherein four different multi-value inverters define the multi-value truth table.

33. The apparatus as claimed in claim 28, wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device.

34. The apparatus as claimed in claim 29 further including a descrambler for descrambling the scrambled multi-value signal, comprising:

a first descrambling multi-value logic device that implements a multi-value logic function, fdc, the first descrambling multi-value logic device having a first and second input and an output;

a descrambling logic circuit having an input and an output;

wherein the scrambled multi-value signal is input to the first input of the first descrambling multi-value logic device and to the input of the descrambling logic circuit and the output of the descrambling logic circuit is input to the second input of the first descrambling multi-value logic device;

wherein the ternary logic function, dc, can be specified by a descrambling ternary truth table having three columns, each of the columns being defined by one of the ternary inverters, i₁ to i₆ and wherein the descrambling logic circuit is the same as the scrambling logic circuit;

whereby a descrambled multi-value signal is provided on the output of the first descrambling multi-value logic device.

35. The apparatus as claimed in claim 34, wherein a column in the descrambling multi-value truth table is defined by:

the same inverter that defines the corresponding column in the scrambling multi-value truth table if the inverter is self reversing; and

a different inverter if the corresponding column in the scrambling multi-value truth table is defined by a reversible inverter that is not self-reversing.

36. The apparatus as claimed in claim 28 wherein:

the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device, and

the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling multi-value logic device, the descrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling multi-value logic device, and wherein the output from the second descrambling multi-value logic device is provided to an input of the first descrambling multi-value logic device and the scrambled version of the multi-value signal is input to the descrambling n-length shift register.

37. A multi-value sequence generator, comprising:

a shift register having a plurality of elements;

a multi-value logic device having a first input, a second input and an output;

wherein an output from a first of the plurality of elements is connected to the first input of the multi-value logic device, an output from a second of the plurality of elements is connected to the second input of the multi-value logic device and the output from the multi-value logic device is connected to an input of one of the plurality of elements.

38. A ternary sequence generator, comprising:

a ternary shift register comprising n serially connected ternary memory elements, n being an integer with value 2 or greater;

a ternary logic device that implements a ternary function, the ternary function being represented by a ternary truth table with three columns of three elements and each column in the truth table being one of six ternary reversible inverters, as long as each column in the truth table is not an identity inverter, the ternary logic device having a first and second input and an output;

wherein an output of a first of the memory elements of the n length shift register is connected to the first input of the ternary logic device and an output of a second of the memory elements of the n-length shift register is connected to the second input of the ternary logic device; and

wherein the output of the ternary logic device is connected to an input of the n-length shift register.

39. The ternary sequence generator as claimed in claim 39, whereby a ternary sequence is generated at the output of any of the n-length shift register memory elements

40. The ternary sequence generator as claimed in claim 39, wherein a multiplier is not used.

42. The method of generating a ternary sequence as claimed in claim 39, whereby a ternary sequence is generated at the output of any of the n-length shift register memory elements

43. The method of generating a ternary sequence as claimed in claim 39, wherein a multiplier is not used.

41. A method of generating a ternary sequence with a ternary shift register having n serially connected ternary memory elements, n being an integer with value 2 or greater and with a ternary logic device that implements a ternary function, the ternary function being represented by a ternary truth table with three columns of three elements and each column in the truth table being one of six ternary reversible inverters, as long as each column in the truth table is not an identity inverter, the ternary logic device having a first and second input and an output, comprising:

outputting a first signal from a first of the memory elements of the n length shift register to the first input of the ternary logic device;

outputting a second signal from a second of the memory elements of the n-length shift register to the second input of the ternary logic device; and

outputting a third signal from the ternary logic device to an input of the n-length shift register.

44. A multi-value sequence generator, comprising:

a multi-value shift register comprising n serially connected multi-value memory elements, n being an integer with value 2 or greater;

a multi-value logic device that implements a multi-value function, the multi-value function being represented by a multi-value truth table with x columns of x elements and each column in the truth table being one of x! multi-value reversible inverters, as long as each column in the truth table is not an identity inverter, the multi-value logic device having a first and second input and an output, x being greater than 3;

wherein an output of a first of the memory elements of the n length shift register is connected to the first input of the multi-value logic device and an output of a second of the memory elements of the n-length shift register is connected to the second input of the multi-value logic device; and

wherein the output of the multi-value logic device is connected to an input of the n-length shift register.

45. The multi-value sequence generator as claimed in claim 44, whereby a multi-value sequence is generated at the output of any of the n-length shift register memory elements.

46. The multi-value sequence generator as claimed in claim 44, wherein a multiplier is not used.

47. A method of generating a multi-value sequence with a multi-value shift register having n serially connected multi-value memory elements, n being an integer with value 2 or greater and with a multi-value logic device that implements a multi-value function, the multi-value function being represented by a multi-value truth table with three columns of three elements and each column in the truth table being one of six multi-value reversible inverters, as long as each column in the truth table is not an identity inverter, the multi-value logic device having a first and second input and an output, comprising:

outputting a first signal from a first of the memory elements of the n length shift register to the first input of the multi-value logic device;

outputting a second signal from a second of the memory elements of the n-length shift register to the second input of the multi-value logic device; and

outputting a third signal from the multi-value logic device to an input of the n-length shift register.

48. The method of generating a multi-value sequence as claimed in claim 47, whereby a multi-value sequence is generated at the output of any of the n-length shift register memory elements.

49. The method of generating a multi-value sequence generator as claimed in claim 47, wherein a multiplier is not used.

50. A ternary sequence generator, comprising:

a ternary shift register having n serially connected ternary memory elements, n being an integer greater than or equal to 2;

p ternary logic devices, each ternary logic device implementing a ternary function, each of the ternary functions being represented by a ternary truth table with three columns of three elements, each of the three columns being defined by one of six ternary reversible inverters such that each column is not defined by an identity inverter;

wherein p is less than or equal to (n−

1);

each of the p ternary logic devices being connected in series between an output of the ternary shift register and the input of the ternary shift register and each of the p ternary logic devices having an input connected to an output of one of the ternary memory elements;

wherein the ternary memory elements providing the output to each of the p ternary logic devices are defined by the presence of a coefficient not equal to zero in an irreducible polynomial over the Galois Field GF(3ⁿ) of degree n with p coefficients not equal to zero.

51. A x-value sequence generator, comprising:

a x-value shift register having n serially connected ternary memory elements, n being an integer greater than or equal to 2;

p x-value logic devices, each x-value logic device implementing a x-value function, each of the x-value functions being represented by a x-value truth table with x columns of x elements, each of the x columns being defined by one of x! reversible inverters such that each column is not defined by an identity inverter;

wherein p is less than or equal to (n−

1);

each of the p x-value logic devices being connected in series between an output of the x-value shift register and the input of the x-value shift register and each of the p x-value logic devices having an input connected to an output of one of the x-value memory elements;

wherein the x-value memory elements providing the output to each of the p x-value logic devices are defined by the presence of a coefficient not equal to zero in an irreducible polynomial over the Galois Field GF(xⁿ) of degree n with p coefficients not equal to zero.

52. A ternary sequence generator that generates a sequence based on the polynomial xⁿ+axⁿ⁻

1+bx<sup>n−

2</sup>+ . . . _—

1, the polynomial having p coefficients, comprising;

a ternary shift register having n serially connected ternary memory elements, n being an integer greater than or equal to 2;

p ternary logic devices, each ternary logic device implementing a ternary function, each of the ternary functions being represented by a ternary truth table with three columns of three elements, each of the three columns being defined by one of six ternary reversible inverters such that each column is not defined by an identity inverter;

wherein p is less than or equal to (n−

1);

each of the p ternary logic devices being connected in series between an output of the ternary shift register and the input of the ternary shift register and each of the p ternary logic devices having an input connected to an output of one of the ternary memory elements;

wherein the ternary memory elements providing the output to each of the p ternary logic devices are defined by the terms of the polynomial having a non-zero coefficient.

53. A method of reducing the component count in a first circuit to generate a second circuit that is equivalent to the first circuit, the first circuit having a ternary logic device having a first input and a second input and a two time multiplier connected to at least to one of the first or second inputs, the ternary logic device implementing a ternary logic function that is defined by a first ternary truth table having three rows and three columns, comprising:

if the multiplier is connected to the first input, then modifying the first ternary truth table by switching two columns in the first ternary truth table;

if the multiplier is connected to the second input, then modifying the ternary truth table by switching two rows in the first ternary truth table;

whereby a second ternary truth table is created from the first ternary truth table and the second circuit can be implemented by a second ternary logic device that implements a function that is defined by the second ternary truth table.

54. A method of reducing the component count in a first circuit to generate a second circuit that is equivalent to the first circuit, the first circuit having a ternary logic device having a first input and a second input and a ternary inverter connected to at least to one of the first or second inputs, the ternary logic device implementing a ternary logic function that is defined by a first ternary truth table having three rows and three columns, comprising:

if the ternary inverter is connected to the first input, then modifying the first ternary truth table by switching two columns in the first ternary truth table if the inverter is self-reversing and not equal to the identity inverter or by switching three columns if the inverter is not self-reversing;

if the ternary inverter is connected to the second input, then modifying the ternary truth table by switching two rows in the first ternary truth table if the inverter is self-reversing and not equal to the identity inverter or by switching three rows if the inverter is not self-reversing;

whereby a second ternary truth table is created from the first ternary truth table and the second circuit can be implemented by a second ternary logic device that implements a function that is defined by the second ternary truth table.

55. An electronic circuit for implementing a ternary logic function that has a first column defined by a first ternary inverter, a second column defined by a second ternary inverter and a third column defined by a third ternary inverter, the electronic circuit processing a ternary logic signal and a second input signal, both signals being able to assume a first state, a second state and a third state, comprising:

a first input for the ternary logic signal;

a second input for the second input signal;

an output;

a first channel including means for inverting the ternary logic signal with the first ternary inverter to generate a first inverted ternary logic signal and for placing the first inverter ternary logic signal on the output, when the second input is in the first state;

a second channel including means for inverting the ternary logic signal with the second ternary inverter to generate a second inverted ternary logic signal and for placing the second inverter ternary logic signal on the output, when the second input is in the second state;

a third channel including means for inverting the ternary logic signal with the third ternary inverter to generate a third inverted ternary logic signal and for placing the third inverter ternary logic signal on the output, when the second input is in the third state.

56. An electronic circuit for implementing a ternary logic function that has a first column defined by a first ternary inverter, a second column defined by a second ternary inverter and a third column defined by a third ternary inverter, the electronic circuit processing a ternary logic signal and a second input signal, both signals being able to assume a first state, a second state and a third state, comprising:

a first input for the ternary logic signal;

a second input for the second input signal;

an output;

a first channel connecting the first input to the output, the first channel having a series connection of the first inverter and a first ternary gate that conducts when the second input is in the first state;

a second channel connecting the first input to the output, the second channel having a series connection of the second inverter and a second ternary gate that conducts when the second input is in the second state;

a third channel connecting the first input to the output, the third channel having a series connection of the third inverter and a third ternary gate that conducts when the second input is in the third state.

57. A method of scrambling an unknown ternary signal with a known ternary signal, the known and unknown ternary signals being able to assume one of three states, comprising:

inputting the unknown ternary signal to a first input of a scrambling ternary logic device;

inputting the known ternary signal to a second input of the scrambling ternary logic device;

wherein the ternary logic function, sc, can be specified by a scrambling ternary truth table having three columns, each of the columns being defined by a ternary inverter, and

outputting a scrambled ternary signal from an output of the scrambling ternary logic device.

58. The method as claimed in claim 57, wherein each column is defined by one of the following ternary inverters i₁ to i₆, as long as each column is not defined by i₁:

i₁ i₂ i₃ i₄ i₅ i₆ 0 0 0 1 1 2 2 1 1 2 0 2 0 1 2 2 1 2 0 1 0

59. The method as claimed in claim 58, wherein at least two different ternary inverters define the scrambling ternary truth table.

60. The method as claimed in claim 58, wherein three different ternary inverters define the scrambling ternary truth table.

61. The method as claimed in claim 58, comprising:

inputting the scrambled ternary signal to a first input of a descrambling ternary logic device;

inputting the known ternary signal to a second input of the descrambling ternary logic device;

the descrambling ternary logic device implementing the ternary logic function, sc, the descrambling ternary logic function being defined by a truth table having three columns of three elements, wherein a column in the descrambling ternary truth table is defined by;

the same inverter that defines the corresponding column in the scrambling ternary truth table if the inverter is i₁, i₂, i₃ or i₆;

the inverter i₅ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₄; and

the inverter i₄ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₅; and

outputting the unknown ternary signal on an output of the descrambling ternary logic device.

62. The method as claimed in claim 60, wherein the known ternary signal specifies one of the columns in the scrambling ternary truth table and in the descrambling ternary truth table.

63. The method as claimed in claim 61, wherein at least two different ternary inverters define the ternary logic function, sc.

64. The method as claimed in claim 61, wherein three different ternary inverters define the ternary logic function, sc.

65. Apparatus for scrambling an unknown ternary signal with a known ternary signal, the known and unknown ternary signals being able to assume one of three states, comprising:

a scrambling ternary logic device having a first input, a second input and an output;

the unknown ternary signal being input to the first input of the scrambling ternary logic device and the known ternary signal being input to the second input of the scrambling ternary logic device;

wherein the scrambling ternary logic device implements a ternary logic function, sc, that is specified by a ternary truth table having three columns, each of the columns being defined by a ternary inverter, and

wherein a scrambled ternary signal is provided at the output of the scrambling ternary logic device.

66. The apparatus as claimed in claim 65, wherein each column is defined by one of the following inverters i₁ to i₆, as long as each column is not defined by i₁:

i₁ i₂ i₃ i₄ i₅ i₆ 0 0 0 1 1 2 2 1 1 2 0 2 0 1 2 2 1 2 0 1 0

67. The apparatus as claimed in claim 66, wherein at least two different ternary inverters define the scrambling ternary truth table.

68. The apparatus as claimed in claim 66, wherein three different ternary inverters define the scrambling ternary truth table.

69. The apparatus as claimed in claim 66, further comprising:

a descrambling ternary logic device having a first input, a second input and an output, the descrambling ternary logic function being defined by a truth table having three columns of the three elements, wherein a column in the descrambling ternary truth table is defined by;

the same inverter that defines the corresponding column in the scrambling ternary inverter is i₁, i₂, i₃ or i₆;

the inverter i₅ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₄; and

the inverter i₄ if the corresponding column in the scrambling ternary truth table is defined by the inverter i₅;

the scrambled ternary signal being input to the first input of the descrambling ternary logic device and the known ternary signal being input to the second input of the descrambling ternary logic device;

wherein the descrambling ternary logic device implements the ternary logic function, sc, and

wherein the unknown ternary signal is provided at the output of the descrambling ternary logic device.

70. The apparatus as claimed in claim 69, wherein the known ternary signal specifies one of the columns in the scrambling ternary truth table and in the descrambling ternary truth table.

71. The apparatus as claimed in claim 70, wherein each column of the scrambling ternary truth table that defines the ternary logic function, sc, is defined by one of the following ternary inverters i₁ to i₆, as long as each column is not defined by i₁:

i₁ i₂ i₃ i₄ I₅ i₆ 0 0 0 1 1 2 2 1 1 2 0 2 0 1 2 2 1 2 0 1 0

72. The apparatus as claimed in claim 71, wherein at least two different ternary inverters define the ternary logic function, sc.

73. The apparatus as claimed in claim 71, wherein three different ternary inverters define the ternary logic function, sc.