Method and structure for determining thermal cycle reliability

• US 20050186689A1
• Filed: 02/20/2004
• Published: 08/25/2005
• Est. Priority Date: 02/20/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Wang, Ping-Chuan, Murray, Conal Eugene, Shaw, Thomas M., McGahay, Vincent J., McLaughlin, Paul Stephen, Gill, Jason Paul, Filippi, Ronald Gene, Rathore, Hazara Singh
• Granted Patent: US 7,098,054 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/0269 for visual or optical inspection
• CPC Class Codes: H05K 1/092 Dispersed materials, e.g. conductive pastes or inks
• CPC Class Codes: Y10S 438/927 Electromigration resistant metallization
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part

Abstract

A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

Claims

1. A method for evaluating reliability of a semiconductor chip structure built by a manufacturing process, comprising the steps of:

building a test structure in accordance with a manufacturing process;

thermal cycling the test structure;

measuring the yield of the test structure; and

evaluating reliability of the semiconductor chip structure built by the manufacturing process based on the yield.

2. The method as recited in claim 1, wherein the yield includes a relative number of electrically functional structures formed by the manufacturing process before thermal cycling.

3. The method as recited in claim 1, further comprising the step of fabricating the test structure to provide a uniform stress condition on one or more structures.

4. The method as recited in claim 1, wherein the step of building includes employing a dual damascene process.

5. The method as recited in claim 4, wherein the step of building includes forming the dual damascene structure with vias having conductive liners along bottoms and sidewalls of the vias.

6. The method as recited in claim 1, wherein the step of building a test structure includes providing a mismatch in a coefficient of thermal expansion (CTE) between metal and dielectric materials.

7. The method as recited in claim 1, wherein the step of building includes building the test structure to provide a bimodal failure distribution having early and late fails during thermal cycle testing.

8. The method as recited in claim 7, wherein the step of evaluating reliability is based on early fails.

9. A method for evaluating reliability of a semiconductor chip structure built by a manufacturing process, comprising the steps of:

building a test structure in accordance with a manufacturing process, which uses materials having mismatches in coefficients of thermal expansion, the test structure including features having predetermined strain values;

thermal cycling the test structure to induce changes or failures of the features;

measuring the yield of the features in the test structure; and

evaluating reliability of the semiconductor chip structure built by the manufacturing process based on the yield.

10. The method as recited in claim 9, wherein the yield includes a relative number of electrically functional features formed by the manufacturing process before thermal cycling.

11. The method as recited in claim 9, further comprising the step of fabricating the test structure to provide a uniform stress condition on one or more of the features.

12. The method as recited in claim 9, wherein the step of building includes employing a dual damascene process to form the features.

13. The method as recited in claim 12, wherein the step of building includes forming dual damascene features with vias having conductive liners along bottoms and sidewalls of the vias.

14. The method as recited in claim 9, wherein the step of building a test structure includes providing a mismatch in a coefficient of thermal expansion (CTE) between metal and dielectric materials.

15. The method as recited in claim 9, wherein the step of building includes building the test structure to provide a bimodal failure distribution having early and late fails.

16. The method as recited in claim 15, wherein the step of evaluating reliability is based on early fails.

17. A test structure used to determine reliability performance, comprising:

a patterned metallization structure having a plurality of interfaces, which provide stress risers;

a dielectric material surrounding the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.

18. The structure as recited in claim 17, wherein the same strain value is across all vias in the test structure.

19. The structure as recited in claim 17, wherein the patterned metallization structure includes a dual damascene structure.

20. The structure as recited in claim 17, further comprising conductive liners along bottoms and sidewalls of vias in the dual damascene structure.

21. The structure as recited in claim 20, wherein the liners include one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) and tungsten (W).

22. The structure as recited in claim 17, wherein the metallization structure includes one of aluminum (Al), copper (Cu), Gold (Au), silver (Ag) and alloys thereof.

23. The structure as recited in claim 17, wherein the dielectric material includes an organic material.

24. The structure as recited in claim 17, wherein the dielectric material includes one of SiLK (trademark of Dow Chemical), polyamide, SiCOH, a nitride and an oxide.

25. The structure as recited in claim 17, wherein the mismatch in CTE between the metallization structure and the dielectric material is greater than about 20 ppm/°

C.

26. The structure as recited in claim 17, wherein the metallization structure includes a stacked via chain having at least two levels of interconnects and vias.

27. The structure as recited in claim 17, further comprising dummy structures not electrically connected to the metallization structure and placed near ends of the test structure to reduce the variation in thermal strain at corner or end vias.

28. The structure as recited in claim 17, wherein the metallization structure is separated from metal pads by a distance to reduce thermal expansion effects caused by the metal pads.

29. The structure as recited in claim 28, wherein the distance between the metallization structure and the bond pads is such that a reduction in thermal strain of any via is within 5% of a maximum value of thermal strain that exists between the metallization structure and the dielectric material for a completely isolated via.

30. The structure as recited in claim 17, wherein the metallization structure further comprises multiple sections electrically connected and separated by a distance to reduce thermal expansion effects caused by adjacent vias.

31. The structure as recited in claim 30, wherein the distance between the sections is such that a reduction in thermal strain of any section is within 5% of a maximum value of thermal strain that exists between the metallization structure and the dielectric material for a completely isolated section of vias.