Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

• US 20050186742A1
• Filed: 02/24/2005
• Published: 08/25/2005
• Est. Priority Date: 02/24/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Won, Lee, Sung-Young, Park, Dong-Gun, Choe, Jeong-Dong, Oh, Chang-Woo
• Application Number:
  US11/065,002
• Publication Number:
  US 20050186742A1
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Claims

1. A FinFET device, comprising:

a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate;

a gate electrode on an upper surface and sidewalls of the channel region; and

first and second source/drain contacts on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode.

2. The device of claim 1, wherein the channel region is narrower than the first and second source/drain regions of the fin-shaped active region.

3. The device of claim 1, further comprising:

a gate insulation layer on the upper surface and sidewalls of the channel region between the gate electrode and the channel region to form a triple-gate FinFET device.

4. The device of claim 3, further comprising:

a capping insulation layer on the upper surface of the channel region between the gate electrode and the channel region to form a double-gate FinFET device.

5. The device of claim 4, wherein the channel region is narrower than the capping insulation layer.

6. The device of claim 1, further comprising:

sidewall spacers on the first and second source/drain regions adjacent opposing sidewalls of the gate electrode.

7. The device of claim 6, wherein the gate electrode comprises a lower gate electrode on the upper surface and sidewalls of the channel region and an upper gate electrode on the lower gate electrode.

8. The device of claim 7, wherein the sidewall spacers respectively comprise an upper sidewall spacer adjacent sidewalls of the upper gate electrode and a lower sidewall spacer adjacent sidewalls of the lower gate electrode.

9. The device of claim 1, wherein the substrate comprises a silicon-on-insulator substrate having a base layer, a buried insulation layer on the base layer, and a semiconductor layer on the buried insulation layer, wherein the fin-shaped active region vertically protrudes from the semiconductor layer.

10. A Fin FET device, comprising:

a semiconductor substrate;

a fin-shaped active region vertically extending from the semiconductor substrate;

a device isolation layer adjacent sidewalls of the fin-shaped active region;

a gate electrode on an upper surface and sidewalls of the fin-shaped active region;

sidewall spacers on sidewalls of the gate electrode; and

source/drain regions in the fin-shaped active region at opposite sides of the gate electrode, wherein upper surfaces and sidewalls of the fin-shaped active region are exposed at the source/drain regions.

11. A method of forming a fin field-effect transistor, comprising:

forming a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate;

forming a gate electrode on an upper surface and sidewalls of the channel region; and

forming first and second source/drain contacts at opposite sides of the gate electrode on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region.

12. The method of claim 11, further comprising:

recessing the sidewalls of the channel region prior to forming the gate electrode such that the channel region is narrower than the first and second source/drain regions of the fin-shaped active region.

13. The method of claim 12, wherein recessing the sidewalls of the channel region comprises isotropically etching the sidewalls of the channel region to narrow the channel region.

14. The method of claim 12, wherein recessing the sidewalls of the channel region comprises:

thermally oxidizing the channel region to form an oxide layer on the upper surface and sidewalls of the channel region; and

removing the oxide layer to narrow the channel region.

15. A method of forming a FinFET, comprising:

forming a fin-shaped active region vertically protruding from a semiconductor substrate;

forming a device isolation layer on the fin-shaped active region, the device isolation layer having a trench therein exposing a first portion of the fin-shaped active region including an upper surface and sidewalls thereof;

forming a gate electrode in the trench on the upper surface and sidewalls of the first portion of the fin-shaped active region;

forming first and second source/drain regions in second portions of the fin-shaped active region at opposite sides of the gate electrode; and

recessing the device isolation layer at opposite sides of the gate electrode to expose upper surfaces and sidewalls of the second portions of the fin-shaped active region.

16. The method of claim 15, further comprising:

forming first and second source/drain contacts on the respective first and second source/drain regions at the exposed upper surface and sidewalls of the second portions of the fin-shaped active region.

17. The method of claim 15, wherein forming the first and second source/drain regions comprises:

implanting dopants into the upper surfaces and sidewalls of the second portions of the fin-shaped active region after recessing the device isolation layer.

18. The method of claim 15, further comprising:

implanting dopants into the first portion of the fin-shaped active region prior to forming the gate electrode to form a channel region therein.

19. The method of claim 15, further comprising:

recessing the sidewalls of the first portion of the fin-shaped active region before forming the gate electrode such that the first portion is narrower than the second portions of the fin-shaped active region.

20. The method of claim 15, wherein forming the device isolation layer comprises:

forming an insulation layer on the substrate including the fin-shaped active region;

recessing the insulation layer by chemical-mechanical polishing to expose the upper surface of the fin-shaped active region;

forming a mask pattern on the insulation layer and the upper surface of the fin-shaped active region, the mask pattern having an opening therein exposing the upper surface of the first portion of the fin-shaped active region and a portion of the insulation layer; and

etching the exposed portion of the insulation layer to define a trench in the insulation layer and to expose the sidewalls of the first portion of the fin-shaped active region.

21. The method of claim 15, further comprising:

forming a gate insulation layer on the upper surface and sidewalls of the first portion of the fin-shaped active region,

wherein forming the gate electrode comprises forming the gate electrode on the gate insulation layer to define a triple-gate FinFET device.

22. The method of claim 21, further comprising:

forming a capping insulation layer on the upper surface of the first portion of the fin-shaped active region,

wherein forming the gate electrode comprises forming the gate electrode on the capping insulation layer on the upper surface and the gate insulation layer on the sidewalls of the first portion of the fin-shaped active region to define a double-gate FinFET device.

23. The method of claim 15, further comprising:

forming sidewall spacers on the first and second source/drain regions adjacent opposing sidewalls of the gate electrode.

24. The method of claim 23, wherein forming the gate electrode comprises:

forming a lower gate electrode on the upper surface and sidewalls of the first portion of the fin-shaped active region; and

forming an upper gate electrode on the lower gate electrode.

25. The method of claim 24, wherein forming the sidewall spacers comprises:

forming upper sidewall spacers adjacent sidewalls of the upper gate electrode; and

forming lower sidewall spacers adjacent sidewalls of the lower gate electrode.