Data bus configuration

• US 20050188181A1
• Filed: 02/05/2004
• Published: 08/25/2005
• Est. Priority Date: 02/05/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Mar, Eugene
• Granted Patent: US 7,047,345 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system includes logic configured for counting transitions between data on a bus and data to be put onto the bus. Where the counted transitions exceed a threshold, the data to be put onto the bus is complemented. As a result, complemented data is put on the bus where the threshold was exceeded and un-complemented data is put on the bus where the threshold was not exceeded.

Claims

1. A system comprising logic configured for:

counting transitions between data on a bus and data to be put onto the bus;

complementing the data to be put onto the bus where the counted transitions exceeds a threshold;

putting complemented data on the bus where the threshold was exceeded; and

putting un-complemented data on the bus where the threshold was not exceeded.

2. The system as recited in claim 1, wherein the logic configured for counting transitions comprises a ripple counter.

3. The system as recited in claim 1, wherein the logic configured for counting transitions comprises a binary tree.

4. The system as recited in claim 1, wherein the logic configured for counting transitions comprises a carry look-a-head counter.

5. The system as recited in claim 1, additionally comprising logic configured for setting the threshold at one-half of a width of the bus.

6. The system as recited in claim 1, additionally comprising logic configured for setting a signal to indicate complemented and un-complemented data.

7. The system as recited in claim 1, additionally comprising logic configured for setting a signal according to a number of transitions relative to the threshold.

8. The system as recited in claim 1, additionally comprising logic configured for:

obtaining data from the bus;

checking a signal to determine if the data has been complemented; and

where the data has been complemented, un-complementing the data.

9. A system comprising logic configured for:

obtaining data from a data bus;

checking a signal to determine if the data has been complemented; and

where the data has been complemented, un-complementing the data.

10. A method of transmitting data, comprising:

counting transitions between data on a bus and data to be put onto the bus;

complementing the data to be put onto the bus where a number of transitions exceeds a threshold;

putting complemented data on the bus where the threshold was exceeded; and

putting un-complemented data on the bus where the threshold was not exceeded.

11. The method as recited in claim 10, wherein counting the transitions comprises counting the transitions using a ripple counter.

12. The method as recited in claim 10, wherein counting the transitions comprises counting the transitions using a binary tree.

13. The method as recited in claim 10, wherein counting the transitions comprises counting the transitions using a carry look-a-head counter.

14. The method as recited in claim 10, additionally comprising setting the threshold at one-half of a width of the bus.

15. The method as recited in claim 10, additionally comprising setting a signal to indicate complemented and un-complemented data.

16. The method as recited in claim 10, additionally comprising:

obtaining data from the bus;

checking a signal to determine if the data has been complemented; and

where the data has been complemented, un-complementing the data.

17. A bus configured for low power consumption and low EMI emissions, comprising:

a transition counter, to count transitions between a first data transmission and a second data transmission and to compare the counted transitions to a threshold;

a data complement module, to complement the second data transmission where the threshold was exceeded;

a driver circuit to change voltages on data lines from the first data transmission to the second data transmission; and

a complement indicator, to operate a signal to indicate if the second data transmission is complemented.

18. The bus of claim 17, wherein the transition counter comprises a ripple counter.

19. The bus of claim 17, wherein the transition counter comprises a binary tree counter.

20. The bus of claim 17, wherein the transition counter comprises a carry look-a-head counter.

21. The bus of claim 17, wherein output of the transition counter controls operation of the data complement module and the complement indicator.

22. The bus of claim 17, additional comprising:

a complement detector communicate to monitor the signal line; and

a data de-complementing module to de-complement the data, if indicated by the signal line.

23. The bus of claim 17, additional comprising:

a complement detector, to detected the signal indicating that the data transmitted is complemented.

24. The bus of claim 17, additional comprising:

a data de-complementing module, to reverse changes made by the data complement module.

25. A system for data transmission, comprising:

means for counting transitions between data on a bus and data to be put onto the bus;

means for complementing the data to be put onto the bus where the counted transitions exceeds a threshold;

means for putting complemented data on the bus where the threshold was exceeded; and

means for putting un-complemented data on the bus where the threshold was not exceeded.

26. The system as recited in claim 25, wherein the means for counting transitions comprises a binary tree.

27. The system as recited in claim 25, additionally comprising means for setting the threshold at one-half of a width of the bus.

28. The system as recited in claim 25, additionally comprising means for setting a signal to indicate complemented and un-complemented data.

29. The system as recited in claim 25, additionally comprising means for setting a signal according to a number of transitions relative to the threshold.

30. A processor-readable medium comprising processor-executable instructions for:

counting transitions between data on a bus and data to be put onto the bus;

complementing the data to be put onto the bus where the counted transitions exceeds a threshold;

putting complemented data on the bus where the threshold was exceeded; and

putting un-complemented data on the bus where the threshold was not exceeded.

31. The processor-readable medium as recited in claim 30, additionally comprising instructions for setting the threshold at one-half of a width of the bus.

32. The processor-readable medium as recited in claim 30, additionally comprising instructions for setting a signal to indicate complemented and un-complemented data.

33. The processor-readable medium as recited in claim 30, additionally comprising instructions for:

obtaining data from the bus;

checking a signal to determine if the data has been complemented; and

where the data has been complemented, un-complementing the data.

34. The processor-readable medium as recited in claim 30, additionally comprising instructions for:

obtaining data from the bus;

checking a signal to determine if the data has been complemented; and

where the data has been complemented, un-complementing the data.

35. A processor-readable medium comprising processor-executable instructions for reading data from a bus, the processor-executable instructions comprising instructions for:

obtaining data from a data bus;

checking a signal to determine if the data has been complemented; and

where the data has been complemented, un-complementing the data.