On-chip storage of secret information as inverse pair

• US 20050188218A1
• Filed: 12/02/2003
• Published: 08/25/2005
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Plunkett, Richard Thomas, Walmsley, Simon Robert
• Granted Patent: US 7,592,829 B2
• Time in Patent Office: Days
• US Class Current: 726/22
• CPC Class Codes: B41J 2/04505 aiming at correcting alignment
• CPC Class Codes: B41J 2/04508 aiming at correcting other parameters
• CPC Class Codes: B41J 2/0451 for detecting failure, e.g. clogging, malfunctioning actuator
• CPC Class Codes: B41J 2/04528 aiming at warming up the head
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/04573 Timing; Delays
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
• CPC Class Codes: B41J 2202/20 Modules
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04N 1/405 Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
• CPC Class Codes: Y10S 707/99933 : Query processing, i.e. searching
• CPC Class Codes: Y10S 707/99939 : Privileged access
• CPC Class Codes: Y10T 29/49401 : Fluid pattern dispersing device making, e.g., ink jet

Abstract

An integrated circuit comprising a processor and memory storing: secret information accessible via a first address, the secret information comprising a string of bit values; an inverse-string accessible via a second address, the inverse-string comprising a string of bit values, wherein each of the bit values in the inverse-string is the logical inverse of a bit value at a corresponding bit position in the secret information, the integrated circuit being programmed with code configured to: (i) receive a request for the secret information; and (ii) test whether the bit-values of the inverse string are the inverse of the bit-values at respective corresponding bit positions of the secret information.

Claims

1. An integrated circuit comprising a processor and memory storing:

secret information accessible via a first address, the secret information comprising a string of bit values;

an inverse-string accessible via a second address, the inverse-string comprising a string of bit values, wherein each of the bit values in the inverse-string is the logical inverse of a bit value at a corresponding bit position in the secret information, the integrated circuit being programmed with code configured to;

(i) receive a request for the secret information; and

(ii) test whether the bit-values of the inverse string are the inverse of the bit-values at respective corresponding bit positions of the secret information.

2. An integrated circuit according to claim 1, configured and programmed to perform a defensive action in the event the test fails.

3. An integrated circuit according to claim 2, wherein the defensive action incudes deleting or destroying some or all of the contents of the memory in the event the test fails.

4. An integrated circuit according to claim 3, wherein the defensive action includes deleting or destroying the secret information and/or the inverse string.

5. An integrated circuit according to claim 3, wherein the defensive action includes preventing the processor from executing software.

6. An integrated circuit according to claim 3, wherein the defensive action includes resetting some or all of logic on the integrated circuit.

7. An integrated circuit according to claim 1, wherein the first and second addresses are at the same address in the memory.

8. An integrated circuit according to claim 7, wherein the string and inverse string are stored at different sub-addresses within the same address.

15. A method of manufacturing a plurality of the integrated circuits defmed in claim 1, comprising the steps, for each of the plurality of integrated circuits, of:

storing the secret information and the inverse string at the first and second addresses in the memory of the integrated circuit; and

storing the code on the integrated circuit;

wherein the first and second addresses are randomly, pseudo-randomly or arbitrarily selected for each of the integrated circuits and the code for each integrated circuit is customised to know the first and second addresses of its secret information and inverse string.

16. A method according to claim 15, wherein the first and second addresses are restricted to one of two potential locations in the memory of each integrated circuit, the secret information and the inverse string for each integrated circuit being allocated to the first and second addresses randomly, pseudo-randomly or arbitrarily.

17. A method according to claim 15, wherein the secret information differs between at least two of the integrated circuits.

9. A method of ensuring validity of secret information stored in a memory in the form of a string of bit values accessible via a first address, the memory also storing an inverse-string accessible via a second address, the inverse-string comprising a string of bit values that are the logical inverses of the bit values at corresponding respective bit positions of the secret information, the method including the steps of:

receiving a request for the secret information; and

testing whether the bit-values of the inverse string are the inverse of the bit-values at respective corresponding bit positions of the secret information.

10. A method according to claim 9, further including the step of performing a defensive action in the event the test fails.

11. A method according to claim 10, wherein the defensive action incudes deleting or destroying some or all of the contents of the memory in the event the test fails.

12. A method according to claim 10, wherein the defensive action includes deleting or destroying the secret information and/or the inverse string.

13. A method according to claim 10, wherein the defensive action includes preventing execution of at least some code.

14. A method according to claim 10, performed by an integrated circuit, wherein the defensive action includes resetting some or all logic on the integrated circuit.