Method of designing semiconductor integrated circuit

• US 20050188340A1
• Filed: 03/15/2005
• Published: 08/25/2005
• Est. Priority Date: 02/20/1996
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takeoka, Sadami
• Granted Patent: US 7,475,378 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G01R 31/318586 with partial scan or non-scannable parts

Abstract

A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Claims

1. A method of designing a semiconductor integrated circuit comprising:

step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function, on the basis of layout information.

2-10. -10. (canceled)

11. A method of designing a semiconductor integrated circuit comprising:

a step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function, on the basis of timing information.

12-14. -14. (canceled)

15. A method of designing a semiconductor integrated circuit comprising:

an element connecting step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes a step of;

selecting one of said output terminals of said first memory element having a maximum driving ability and connecting said selected output terminal with said scan data input terminal of said second memory element.

16. The method of designing a semiconductor integrated circuit of claim 15,

wherein said element connecting step further includes a step of discriminating whether or not there exist any unconnected output terminals among said output terminals of said first memory element, and in the case where unconnected output terminals exist, selecting one of said unconnected output terminals having a maximum driving ability.

17. A method of designing a semiconductor integrated circuit comprising:

an element connecting step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes a step of;

connecting one of said output terminals of said first memory element having a design margin larger than a predetermined value with said scan data input terminal of said second memory element, said design margin being obtained as a difference between one cycle time of a clock signal and propagation time required for a signal to travel from each of said output terminals of said first memory element to another memory element or an external output port.

18. (canceled)

19. A method of designing a semiconductor integrated circuit comprising:

an element connecting step of connecting one of plural output terminals of a first memory element having a scan data input terminal with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes a step of;

selecting one of said output terminals of said first memory element having maximum delay time of a signal received at said scan data input terminal of said first memory element and connecting said selected output terminal with said scan data input terminal of said second memory element.

20. A method of designing a semiconductor integrated circuit comprising:

an element connecting step of connecting one of plural output terminals of a first memory element having a scan data input terminal with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes a step of;

selecting one of said output terminals of said first element having delay time of a signal received at said scan data input terminal of said first memory element larger than a predetermined value and connecting said selected output terminal with said scan data input terminal of said second memory element.