Charge trapping memory cell and fabrication method

• US 20050189582A1
• Filed: 02/10/2005
• Published: 09/01/2005
• Est. Priority Date: 02/10/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Mikolajick, Thomas
• Granted Patent: US 7,227,219 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for charge trapping and comprising a storage layer (12) between boundary layers (11, 13). The first gate electrode (4) and the second gate electrode (5) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (10). Source/drain regions (3) are arranged on the top side laterally with respect to the trenches. Word lines (6), source/drain lines and control gate lines are present for the electrical driving.

Claims

1. A charge trapping memory cell comprising:

a well in a semiconductor body, said well being doped to a first conductivity type,

a source region and a drain region formed at a top side of the semiconductor body and doped to a second conductivity type that is opposite the first conductivity type;

a trench formed in the semiconductor body, said trench extending into the doped well below the source and drain regions;

a gate electrode, which is electrically insulated from the well by a gate dielectric, the gate electrode being arranged as a first gate electrode in the trench and at least in a bottom portion of the trench;

a second gate electrode arranged in the trench above the first gate electrode and electrically insulated from the first gate electrode; and

a storage layer sequence comprising a storage layer provided for charge trapping between boundary layers, at least portions of the storage layer sequence being arranged between the second gate electrode and the doped well and/or between the second gate electrode and the source and drain regions.

3. The memory cell as claimed in claim 1, wherein the first gate electrode and the second gate electrode are insulated from one another by a portion of the storage layer sequence.

4. The memory cell as claimed in claim 1, wherein a portion of the storage layer sequence reaches as far as an upper edge of the first gate electrode.

5. The charge trapping memory cell of claim 1, wherein the storage layer sequence comprises a nitride layer sandwiched between first and second oxide layers.

6. The charge trapping memory cell of claim 1, wherein the gate electrode comprises polysilicon.

7. The charge trapping memory cell of claim 1, wherein the semiconductor body comprises a semiconductor substrate.

8. The charge trapping memory cell of claim 1, wherein portions of the storage layer sequence are arranged between the second gate electrode and the doped well.

9. The charge trapping memory cell of claim 8, wherein portions of the storage layer sequence are arranged between the second gate electrode and the source and drain regions.

10. The charge trapping memory cell of claim 1, wherein portions of the storage layer sequence are arranged between the second gate electrode and the source and drain regions.

2. The charge trapping memory cell of claim l and ftirther comprising:

a word line coupled to the second gate electrode;

source/drain lines coupled to the source and drain regions; and

a control gate coupled to the first gate electrode.

11. A method for fabricating a memory cell array of charge trapping memory cells, the method comprising:

forming a doped well in a semiconductor body;

forming source/drain regions by implanting dopants of a conductivity type opposite to that of the well at a top side of the semiconductor body;

forming trenches arranged parallel at a distance from one another at the top side, said trenches extending into the well;

forming a gate dielectric layer in lower regions of inner areas of the trenches;

introducing an electrically conductive material into the trenches, said material, in lower portions of the trenches, being provided as first gate electrode and as control gate lines;

removing the electrically conductive material apart from the portions provided for the first gate electrodes and the control gate lines;

providing a storage layer sequence for charge trapping on the first gate electrodes and on inner walls of the trenches;

introducing a second electrically conductive material into the trenches, said material being provided as second gate electrodes; and

patterning the second electrically conductive material to form second gate electrodes.

12. The method as claimed in claim 11, wherein patterning the second electrically conductive material further forms word lines.

13. The method as claimed in claim 11, wherein providing a storage layer sequence comprises removing the gate dielectric layer formed above the first gate electrodes and then forming the storage layer sequence.

14. The method as claimed in claim 11, wherein introducing electrically conductive material comprises depositing polysilicon into the trenches, and wherein providing a storage layer sequence comprises oxidizing the polysilicon on the top side and then fabricating the storage layer sequence with the inclusion of the gate dielectric layer.

15. The method as claimed in claim 11, and between providing the storage layer sequence and introducing the second electrically conductive material, the method further comprising:

forming an auxiliary layer into the trenches;

removing the storage layer sequence above the auxiliary layer; and

removing the auxiliary layer.

16. The method as claimed in claim 11, and between providing the storage layer sequence and introducing the second electrically conductive material, the method further comprising:

etching a spacer to remove the storage layer sequence on the first gate electrodes and the control gate lines with the exception of an edge region; and

subsequently depositing a further dielectric that is provided for the purpose of electrically insulating the first gate electrodes from the second gate electrodes and the source/drain regions from the word lines.

17. The method as claimed in claim 11, and further comprising:

removing the second electrically conductive material from the trenches at the edge of the memory cell array;

removing dielectric present on the control gate lines;

introducing a third electrically conductive material that is contact-connected with the control gate lines; and

patterning said third electrically conductive material on the top side to form terminal contacts.

18. The method as claimed in claim 11, and further comprising:

between providing the storage layer sequence and introducing the second electrically conductive material, carrying out a spacer etching at the edge of the memory cell array, said spacer etching removing the storage layer sequence on the control gate lines with the exception of an edge region;

applying the second electrically conductive material to the control gate lines as contacts at the edge of the memory cell array; and

patterning the second electrically conductive material at the edge of the memory cell array on the top side to form terminal contacts.

19. The method as claimed in claim 11, wherein the electrically conductive material comprises the same material as the second electrically conductive material.

20. The method as claimed in claim 19, wherein the electrically conductive material and the second electrically conductive material both comprise polysilicon.