Semiconductor device comprising transistor pair isolated by trench isolation

• US 20050189595A1
• Filed: 08/18/2004
• Published: 09/01/2005
• Est. Priority Date: 02/26/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Takaramoto, Toshiharu, Okamoto, Atsushi
• Granted Patent: US 7,598,541 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H03M 1/745 with weighted currents

Abstract

A semiconductor device has transistors (P1,P10,P11) formed in an active region (22) isolated by a trench isolation region, and a predetermined circuit including a first and second transistors (P10,P11) that require symmetry or relativity characteristics, wherein the distances (S1) between a gate electrode and one end of the active region on a source side viewed from the gate electrode in the first and second transistor are substantially same, and the distances (D1) between a gate electrode and one end of the active region on a drain side viewed from the gate electrode in the first and second transistor are substantially same. The predetermined circuit includes, for example, a current mirror circuit that has a transistor pair of which gate is commonly connected, and a differential circuit that has a transistor pair whose sources are commonly connected, where an input signal is supplied to the gate, and an output signal is generated in the drain.

Claims

1. A semiconductor device comprising:

transistors formed in an active region isolated by a trench isolation region; and

a predetermined circuit including first and second transistors that have symmetry or relative characteristics,

wherein distances between a gate electrode and an end of said active region on a source side in said first and second transistors are substantially same, and distances between a gate electrode and an end of said active region on a drain side in said first and second transistors are substantially same.

2. The semiconductor device according to claim 1, wherein

said predetermined circuit includes either a current mirror circuit having a transistor pair of which gates are commonly connected, or a differential circuit having a transistor pair of which sources are commonly connected, one of which gates an input signal is supplied to, and one of which drains an output signal is output to.

3. The semiconductor device according to claim 2, wherein

said predetermined circuit further comprises either a differential amplification circuit having said current mirror circuit and said differential circuit, or a digital analog conversion circuit having a plurality of sets of said current mirror circuit and said differential circuit of which gates a digital signal is supplied to.

4. The semiconductor device according to any of claims 1 to 3, wherein

said first and second transistors are respectively formed in first and second active regions surrounded respectively by the trench isolation region,

single gate electrodes are formed in said first and second active regions respectively, said distances on the source side in said first and second transistors are formed to be substantially the same, said distances on the drain side in said first and second transistors are formed to be substantially the same.

5. The semiconductor device according to claim 4, wherein said same distance on said drain side and said same distance on said source side are of different length.

6. The semiconductor device according to any of claims 1 to 3, wherein

said first and second transistors are formed in a common active region surrounded by the trench isolation region,

a single gate electrode pair including first and second gate electrodes is formed in said common active region, where the distance from a first end of said active region to said first gate electrode and the distance from a second end, at the opposite side of said first end, of said active region to said second gate electrode are substantially the same, and a region between said first and second gate electrodes of said active region is a common source or drain region of said first and second transistors.

7. The semiconductor device according to any of claim 1 to claim 3, wherein

said first and second transistors are formed in a plurality of active regions surrounded respectively by the a trench isolation region,

a single gate electrode pair including first and second gate electrodes is formed in each active region, the distance from a first end of said active region to said first gate electrode and the distance from a second end, at the opposite side of said first end, of said active region to said second gate electrode are substantially the same, and

said first or second transistor is constructed by combining said first and second gate electrodes.

8. The semiconductor device according to any of claims 1 to 3, wherein

said first and second transistors are formed in a plurality of active regions surrounded respectively by the trench isolation region,

each active region includes a first sub-active region that extends in a first direction, and a second sub-active region that extends in a second direction that crosses with said first direction in a crossing region of said first sub-active region, and forms a cross-shape with said first and second sub-active regions,

in said first sub-active region, a single gate electrode pair including first and second gate electrodes is formed between a first end of said first sub-active region and said crossing region, and between a second end, at the opposite side of said first end, and said crossing region, and the distance from said first end to said first gate electrode and the distance from said second end to said second gate electrode are substantially the same,

in said second sub-active region, a single gate electrode pair including third and fourth gate electrodes is formed between a first end of said second sub-active region and said crossing region, and between a second end, at the opposite side of said first end, and said crossing region, and the distance from said first end to said third gate electrode and the distance from said second end to said fourth gate electrode are substantially the same, and

said first or second transistor is constructed by combining said first to fourth gate electrodes.

9. The semiconductor device according to any of claims 1 to 3, wherein

said first and second transistors are formed in a plurality of active regions surrounded respectively by the trench isolation region,

each active region includes a first sub-active region that extends in a first direction, and a second sub-active region that extends in a second direction that crosses with said first direction in a crossing region of said first sub-active region, and forms an L-shape with said first and second sub-active regions,

in said first sub-active region, a single gate electrode pair including first and second gate electrodes is formed in said first sub-active region excluding said crossing region of said first sub-active region, and the distance from a first end of said first sub-active region to said first gate electrode, and the distance from a second end, at the opposite side of said first end, to said second gate electrode are substantially the same,

in said second sub-active region, a single gate electrode pair including third and fourth gate electrodes is formed in said second sub-active region excluding said crossing region of said second sub-active region, and the distance from a first end of said second sub-active region to said third gate electrode and the distance from a second end, at the opposite side of said first end, to said fourth gate electrode are substantially the same, and

said first or second transistor is constructed by combining said first to fourth gate electrodes.

10. The semiconductor device according to claim 9, wherein said first or second active region has a pair of L-shapes that is constructed by said first and second sub-active regions, and said pair of L-shapes forms a rectangular shape.

11. The semiconductor device according to claim 8, wherein a plurality of gate electrodes in said first or second active region is constructed by common electrodes respectively.

12. The semiconductor device according to claim 8, wherein said first and second transistors included in said current mirror circuit use a different number of first to fourth gate electrodes.