Upper-layer metal power standard cell

• US 20050189607A1
• Filed: 02/18/2005
• Published: 09/01/2005
• Est. Priority Date: 02/20/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshida, Takeshi, Urakawa, Yukihiro
• Granted Patent: US 7,501,689 B2
• Time in Patent Office: Days
• US Class Current: 257/502
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An upper-layer metal power standard cell comprises: a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell; a transistor element layer which is formed in a predetermined arrangement on a circuit substrate under the basic power metal layer; and an inner wire layer which supplies the power voltage to the transistor element layer disposed under the basic power metal layer disposed in the upper layer from the basic power metal layer.

Claims

1. An upper-layer metal power standard cell comprising:

a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell;

a transistor element layer which is formed in a predetermined arrangement on a circuit substrate under the basic power metal layer; and

an inner wire layer which supplies the power voltage to the transistor element layer disposed under the basic power metal layer disposed in the upper layer from the basic power metal layer.

2. The upper-layer metal power standard cell according to claim 1, further comprising:

an underlayer in which the compacted transistor element layer and inner wire layer are formed on the circuit substrate; and

an upper-layer basic power metal layer disposed in an upper layer of the underlayer and connected to the inner wire layer,

wherein the transistor element layer and the inner wire layer formed in a first layer which is the underlayer are arranged in each standard cell, and a second layer is disposed as the upper-layer basic power metal layer for a plurality of standard cells.

3. The upper-layer metal power standard cell according to claim 1, further comprising:

an underlayer in which the resized transistor element layer and inner wire layer are formed on the circuit substrate; and

an upper-layer basic power metal layer disposed in an upper layer of the underlayer and connected to the inner wire layer,

wherein the transistor element layer and the inner wire layer formed in a first layer which is the underlayer are arranged in each standard cell, and a second layer is disposed as the upper-layer basic power metal layer for a plurality of standard cells.

4. The upper-layer metal power standard cell according to claim 1,

wherein the upper-layer basic power metal layer comprises:

a basic power supply metal layer; and

a basic power ground metal layer extended in the same direction and disposed facing each other, the inner wire or a polycrystalline silicon layer for forming a transistor element are disposed in an underlayer formed under basic power supply and ground metal layers of upper layers on the semiconductor substrate, an end portion side of the underlayer, and the upper-layer basic power metal layer have a range superimposed in a depth direction of the cell, and the upper-layer basic power metal layer is electrically connected to the inner wire layer constituting the underlayer.

5. The upper-layer metal power standard cell according to claim 4,

wherein the underlayer including the polycrystalline silicon layer and the inner wire are formed in a first layer counted from the substrate, the upper-layer basic power metal layer is formed in a second layer counted from the substrate, the first layer is electrically connected to the second layer, and a power is supplied to the inner wire and the transistor element from the upper-layer basic power metal layer.

6. The upper-layer metal power standard cell according to claim 4,

wherein the underlayer including the polycrystalline silicon layer and the inner wire layer is formed in a first layer counted from the substrate, the upper-layer basic power metal layer is formed in a second layer counted from the substrate, contacts are formed at predetermined intervals in the inner wire layer of the first layer, a portion of the inner wire layer in which any contact is not formed is compacted, the first layer is compacted in the other direction crossing the one direction at right angles to thereby compact the first layer, and the upper-layer basic power metal layer of the second layer is formed facing the compacted first layer in the one direction.

7. The upper-layer metal power standard cell according to claim 4,

wherein the underlayer including the polycrystalline silicon layer and the inner wire layer is formed in a first layer counted from the substrate, the upper-layer basic power metal layer is formed in a second layer counted from the substrate, contacts are formed at predetermined intervals in the inner wire layer of the first layer, the contact is formed in a portion of the inner wire layer in which any contact is not formed to thereby change a size of the first layer, accordingly the first layer is resized, and the upper-layer basic power metal layer of the second layer is disposed facing the resized first layer, and formed in one direction.

8. The upper-layer metal power standard cell according to claim 7,

wherein the first layer is extended in the other direction of the underlayer of the metal layer centering on the ground power metal layer which is one of the upper-layer basic power metal layers extended in one direction, and other end portions of the first layer positioned under the ground power metal layer are formed in underlayers of two parallel power supply metal layers which are other upper-layer basic power metal layers of the second layer.

9. The upper-layer metal power standard cell according to claim 8,

wherein an input terminal for supplying a signal to the inner wire and an output terminal for outputting the signal from the inner wire are disposed substantially in middles of other directions in two standard cells comprising power supply metal layers which are disposed at predetermined distances outside the ground power metal layer extended in a center of the other direction and which are extended in one direction, and positions in which the ground power metal layers and the power supply metal layers are formed in two standard cells disposed continuously in one direction, and positions in which the input and output terminals in the two standard cells are formed are aligned and disposed on one straight line.

10. The upper-layer metal power standard cell according to claim 6, further comprising in a mixed manner:

a circuit arrangement in which a plurality of standard cells are arranged in the other direction and in which intervals of the power supply metal layers and the ground metal layers are set to be constant, even when densities of the transistor element layers and the inner wire layers of the second layers in two adjacent standard cells are different from each other and in which a plurality of upper-layer metal power standard cells having an equal size are arranged; and

a circuit arrangement in which compactable upper-layer metal power standard cells are compacted to thereby set sizes of two upper-layer metal power standard cells disposed adjacent in the other direction in a case where the densities are different.

11. The upper-layer metal power standard cell according to claim 10,

wherein an interval of basic power metal layers which are the second layers determined by disposing a densest circuit arrangement in the first layer is set using the densest circuit arrangement as a reference to thereby set and form a power metal layer of the second layer in a circuit arrangement in which the densities of the transistor element and the inner wire of the first layer disposed in the other direction are different.

12. The upper-layer metal power standard cell according to claim 11, further comprising:

a plurality of standard cells having, in a mixed manner, a first size in which the interval of the basic power metal layer determined by disposing a densest circuit arrangement in the first layer is set using the densest circuit arrangement as a reference to thereby set a power metal layer of the second layer, and a second size in which an interval of the basic power metal layer determined by disposing the circuit arrangement compacted by a predetermined amount in the first layer is set with respect to a circuit arrangement having a compactable density in the first layer to thereby set a power metal layer of the second layer in a case where the first layers of a plurality of cells arranged in the other direction have transistor elements and inner wires arranged with different densities.

13. The upper-layer metal power standard cell according to claim 1,

wherein a plurality of standard cells are arranged in the one direction and the other direction, intervals of the power supply metal layer and the ground metal layer in the one direction and the other direction are set to be constant even when densities of the transistor element layer and the inner wire layer of the second layer are different in the other direction in the standard cells arranged in the one direction and the other direction, and a plurality of cells all comprise upper-layer metal power standard cells having an equal size.

14. The upper-layer metal power standard cell according to claim 13, further comprising:

a second layer in which an interval of the power supply metal layer and the power ground metal layer is set to be constant in the other direction and which is disposed in the one direction; and

a first layer constituting an underlayer of the second layer, and comprising a transistor element layer and an inner wire layer disposed in the other direction under the power supply and ground metal layers.

15. The upper-layer metal power standard cell according to claim 13, further comprising:

a plurality of standard cells having an equal size compacted and resized by a circuit arrangement in the first layers of a plurality of cells determined by an equal size which is a maxim size of each cell capable of being reduced at the maximum, a basic power metal layer of a second layer disposed at an interval in accordance with the circuit arrangement of the first layers, in a circuit arrangement in which a plurality of standard cells having different densities of the circuit arrangement of the first layer are arranged in the other direction and the one direction and in which the first layer of each of the plurality of cells is capable of being compacted and resized.

16. A method of manufacturing an upper-layer metal power standard cell comprising:

synthesizing a circuit to be designed as a standard cell;

placing a transistor element and a signal wire layer constituting a circuit on an underlayer of a semiconductor substrate based on the synthesized circuit;

preparing a replaceable table with respect to placing information of the underlayer based on height information of the standard cell and information of a transistor length; and

placing an upper-layer basic power metal layer in a predetermined position on the underlayer, and simulating operation speed information and cell bonding information in the transistor element and the signal wire layer in an allowable range of the replaceable table.

17. The method of manufacturing the upper-layer metal power standard cell according to claim 16, further comprising:

arranging a plurality of formed standard cells in one direction;

arranging a plurality of standard cells in the other direction crossing the one direction at right angles;

arranging elements and wires of the underlayer over both the one direction and the other direction; and

thereafter disposing the upper-layer power metal layer on the underlayer.

18. The method of manufacturing the upper-layer metal power standard cell according to claim 16, further comprising:

synthesizing a circuit to be designed in order to realize a function of a circuit to use;

placing a first layer which is an underlayer including an element/wire layer on a semiconductor substrate;

compacting the element in advance;

checking replacement of element arrangement;

actually replacing the element arrangement in a case where there is not any problem in a result of the replacement check;

modifying an only changed portion without influencing a layout portion in a case where a part of a logical circuit is changed, analyzing delay at a time when layout design ends in order to improve performance, and optimizing delay or area by insertion of a buffer or division of a fan-out; and

checking compaction of a transistor element.

19. An area compression apparatus comprising:

a placing unit configured to arrange standard cells based on predetermined placing information concerning a circuit synthesized using the standard cells;

a changeable information generation unit configured to prepare changeable information including changeable allowable values of a height and a transistor length of the standard cell with respect to the placing information of the standard cells, obtained from the placing unit, based on height information of each of the arranged standard cells and the standard cell disposed in the vicinity, and information of transistor lengths described in each of the arranged standard cells and the standard cell disposed in the vicinity; and

an area compression unit configured to change the height of the standard cell to thereby compress a circuit area in a range of the allowable amount included in the changeable information.