LSI package, LSI element testing method, and semiconductor device manufacturing method

• US 20050189649A1
• Filed: 04/25/2005
• Published: 09/01/2005
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Maruyama, Shigeyuki, Tashiro, Kazuhiro, Nishino, Toru
• Granted Patent: US 7,145,250 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An LSI package comprises an LSI element and a wiring board. The plurality of pin terminals of the LSI element each includes a first conductive layer and a second conductive layer superposed on the first conductive layer. The plurality of pin terminals of the wiring board each includes a third conductive layer joined to the second conductive layer, and the wiring board further comprises outer joining terminals. The first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer. The LSI element is tested using the outer joining terminals of the wiring board. The second conductive layer and third conductive layer are joined to attain a metallic bond through aggregation derived from pressure, and are reliably brought into electrical contact with each other for a test. After the test is completed, the terminals of the LSI element are peeled off from the terminals of the wiring board. At this time, the second conductive layer is transferred to the third conductive layer, and the first conductive layer is left intact in each of the terminals of the LSI element. The LSI element is then mounted on another wiring board.

Claims

1. An LSI package comprising:

at least one LSI element having a plurality of pin terminals; and

a wiring board having a plurality of pin terminals, wherein;

each of the plurality of terminals of the LSI element includes a first conductive layer and a second conductive layer superposed on the first conductive layer;

each of the plurality of terminals of the wiring board includes a third conductive layer joined with the second conductive layer of each of the terminals of the LSI element;

the first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer; and

the wiring board further includes a plurality of outer joining terminals connected to the plurality of pin terminals of the wiring board with wires.

2. An LSI package according to claim 1, wherein the second conductive layer of each of the terminals of the LSI element and the third conductive layer of each of the terminals of the wiring board are joined to attain metallic bond through aggregation derived from pressure.

3. An LSI package according to claim 2, wherein an interface on which the metallic bond is attained through aggregation derived from pressure does not contain a layer of impurities (an oxide or an organic compound) because the surfaces of the conductive layers that are cleaned before being pressured are joined to attain the metallic bond.

4. An LSI package according to claim 1, wherein the pitch between adjoining ones of the outer joining terminals of the wiring board is larger than the pitch between adjoining ones of the terminals of the LSI element.

5. An LSI package according to claim 1, wherein the hardness of a material made into the second conductive layer of each of the terminals of the LSI element is higher than the hardness of a material made into the first conductive layer.

6. An LSI package according to claim 1, wherein the tensile strength of the material made into the second conductive layer of each of the terminals of the LSI element is greater than the tensile strength of the material made into the first conductive layer.

7. An LSI package according to claim 1, wherein the second conductive layer of each of the terminals of the LSI element is smaller than the third conductive layer of each of the terminals of the wiring board.

8. An LSI package according to claim 1, wherein the LSI element and wiring board are further provided with a reinforcement member.

9. An LSI package according to claim 6, wherein the reinforcement member includes an adhesive that can be peeled off.

10. An LSI package according to claim 1, wherein an electronic part for supporting the action of the LSI element or assisting in testing the action of the LSI element is mounted on the wiring board.

11. An LSI element testing method comprising the steps of:

providing an LSI element with a plurality of pin terminals each including a first conductive layer and a second conductive layer superposed on the first conductive layer;

forming on a wiring board a plurality of pin terminals each including a third conductive layer, and a plurality of outer joining terminals connected to the plurality of pin terminals with wires;

joining the plurality of terminals of the LSI element with the plurality of terminals of the wiring board so that the second conductive layers will be bonded to the third conductive layers; and

testing the LSI element using the plurality of outer joining terminals of the wiring board, wherein;

the first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer.

12. A semiconductor device manufacturing method comprising the steps of:

providing an LSI element with a plurality of pin terminals each including a first conductive layer and a second conductive layer superposed on the first conductive layer;

forming on a wiring board a plurality of pin terminals each including a third conductive layer, and a plurality of outer joining terminals connected to the plurality of pin terminals with wires;

joining the plurality of terminals of the LSI element with the plurality of terminals of the wiring board so that the second conductive layers will be bonded to the third conductive layers;

testing the LSI element using the plurality of outer joining terminals of the wiring board;

transporting the LSI element and wiring board to a position different from a position of testing;

peeling off the plurality of terminals of the LSI element from the plurality of terminals of the wiring board; and

joining the plurality of terminals of the LSI element with the plurality of terminals of another wiring board, wherein;

the first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer.

13. A semiconductor device manufacturing method according to claim 12, further comprising a step of cleaning at least the surfaces of the second conductive layers of the terminals of the LSI element and the surfaces of the third conductive layers of the terminals of the wiring board prior to the step of joining the plurality of terminals of the LSI element with the plurality of terminals of the wiring board.

14. A semiconductor device manufacturing method according to claim 13, wherein the cleaning step refers to an ashing step.

15. A semiconductor device manufacturing method according to claim 19, wherein at the peeling step, the second conductive layers of the terminals of the LSI element are stuck on to the third conductive layers of the terminals of the wiring board, and the first conductive layers alone are substantially left intact in the respective terminals of the LSI element.

16. A semiconductor device manufacturing method according to claim 12, wherein at the step of joining the plurality of terminals of the LSI element with the plurality of terminals of the wiring board, the second conductive layers of the terminals of the LSI element and the third conductive layers of the terminals of the wiring board are joined to attain metallic bond through aggregation derived from pressure.

17. A semiconductor device manufacturing method according to claim 12, wherein at least at the transporting step, the LSI element and wiring board are further provided with a reinforcement member.

18. A semiconductor device manufacturing method according to claim 17, wherein the reinforcement member includes an adhesive that can be peeled off.

19. A semiconductor device manufacturing method according to claim 12, wherein at the step of joining the plurality of terminals of the LSI element with the plurality of terminals of another wiring board, the plurality of terminals of the LSI element is joined to the plurality of terminals of the wiring board by performing wire bonding.

20. A semiconductor device manufacturing method according to claim 12, wherein at the step of joining the plurality of terminals of the LSI element with the plurality of terminals of another wiring board, the plurality of terminals of the LSI element is joined to the plurality of terminals of the wiring board via bumps.